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openwrt/target/linux
Felix Fietkau c75a0e86b1 ar71xx: add mask and shift for RXD/RDV bits in AR934X register file
The commit r38948 ("ag71xx: add F1E specific feature bit definitions to AR934X
register file") introduced definitions for some bits in the RDV/RXD part of the
ETH_CFG register of AR934x. These are incomplete because ETH_RXDV_DELAY is
specified as 17:16 and ETH_RXD_DELAY is specified 15:14. The original commit
only specified the lower bits. The upper bits also have to be unset when the
lower bits should only be set.

Signed-off-by: Sven Eckelmann <sven@open-mesh.com>

SVN-Revision: 45522
2015-04-20 15:00:41 +00:00
..
adm5120
adm8668
ar7
ar71xx ar71xx: add mask and shift for RXD/RDV bits in AR934X register file 2015-04-20 15:00:41 +00:00
arm64
at91
ath25
au1000
bcm53xx
brcm47xx
brcm63xx
brcm2708
cns3xxx
gemini
generic
imx6
ipq806x
ixp4xx
kirkwood
lantiq
malta
mcs814x
mpc85xx
mvebu
mxs
netlogic
octeon
omap
omap24xx
orion
oxnas
ppc40x
ppc44x
pxa
ramips
rb532
realview
sunxi
uml
x86
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