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fb2c6e9d4d
Removed because they are upstream: generic/backport-5.15/704-15-v5.19-net-mtk_eth_soc-move-MAC_MCR-setting-to-mac_finish.patch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=linux-5.15.y&id=c5c0760adc260d55265c086b9efb350ea6dda38b generic/pending-5.15/735-net-mediatek-mtk_eth_soc-release-MAC_MCR_FORCE_LINK-.patch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=linux-5.15.y&id=448cc8b5f743985f6d1d98aa4efb386fef4c3bf2 generic/pending-5.15/736-net-ethernet-mtk_eth_soc-fix-PPE-hanging-issue.patch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=linux-5.15.y&id=9fcadd125044007351905d40c405fadc2d3bb6d6 Add new configuration symbols for tegra target. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
142 lines
5.2 KiB
Diff
142 lines
5.2 KiB
Diff
From 8cfa2576d79f9379d167a8994f0fca935c07a8bc Mon Sep 17 00:00:00 2001
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From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
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Date: Sat, 22 Jul 2023 21:32:49 +0100
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Subject: [PATCH 096/250] net: ethernet: mtk_eth_soc: remove incorrect PLL
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configuration
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MT7623 GMAC0 attempts to configure the system clocking according to the
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required speed in the .mac_config callback for non-SGMII, non-baseX and
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non-TRGMII modes.
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state->speed setting has never been reliable in the .mac_config
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callback - there are cases where this is not the link speed,
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particularly via ethtool paths, so this has always been unreliable (as
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detailed in phylink's documentation.)
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There is the additional issue that mtk_gmac0_rgmii_adjust() will only
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be called if state->interface changes, which means it only configures
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the system clocking on the very first .mac_config call, which will be
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made when the network device is first brought up before any link is
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established.
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Essentially, this code is incredibly buggy, and probably never worked.
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Moreover, checking the in-kernel DT files, it seems no platform makes
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use of this code path.
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Therefore, let's remove it, and disable interface modes for port 0 that
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are not SGMII, 1000base-X, 2500base-X or TRGMII on the MT7623.
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Reviewed-by: Daniel Golle <daniel@makrotopia.org>
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Tested-by: Daniel Golle <daniel@makrotopia.org>
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Tested-by: Frank Wunderlich <frank-w@public-files.de>
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Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
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Signed-off-by: Paolo Abeni <pabeni@redhat.com>
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---
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drivers/net/ethernet/mediatek/mtk_eth_soc.c | 54 ++++++---------------
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drivers/net/ethernet/mediatek/mtk_eth_soc.h | 1 +
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2 files changed, 17 insertions(+), 38 deletions(-)
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--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
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+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
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@@ -309,7 +309,7 @@ static int mt7621_gmac0_rgmii_adjust(str
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}
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static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth,
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- phy_interface_t interface, int speed)
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+ phy_interface_t interface)
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{
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u32 val;
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int ret;
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@@ -323,26 +323,7 @@ static void mtk_gmac0_rgmii_adjust(struc
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return;
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}
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- val = (speed == SPEED_1000) ?
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- INTF_MODE_RGMII_1000 : INTF_MODE_RGMII_10_100;
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- mtk_w32(eth, val, INTF_MODE);
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-
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- regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0,
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- ETHSYS_TRGMII_CLK_SEL362_5,
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- ETHSYS_TRGMII_CLK_SEL362_5);
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-
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- val = (speed == SPEED_1000) ? 250000000 : 500000000;
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- ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val);
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- if (ret)
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- dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret);
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-
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- val = (speed == SPEED_1000) ?
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- RCK_CTRL_RGMII_1000 : RCK_CTRL_RGMII_10_100;
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- mtk_w32(eth, val, TRGMII_RCK_CTRL);
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-
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- val = (speed == SPEED_1000) ?
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- TCK_CTRL_RGMII_1000 : TCK_CTRL_RGMII_10_100;
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- mtk_w32(eth, val, TRGMII_TCK_CTRL);
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+ dev_err(eth->dev, "Missing PLL configuration, ethernet may not work\n");
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}
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static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config,
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@@ -428,17 +409,8 @@ static void mtk_mac_config(struct phylin
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state->interface))
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goto err_phy;
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} else {
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- /* FIXME: this is incorrect. Not only does it
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- * use state->speed (which is not guaranteed
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- * to be correct) but it also makes use of it
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- * in a code path that will only be reachable
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- * when the PHY interface mode changes, not
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- * when the speed changes. Consequently, RGMII
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- * is probably broken.
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- */
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mtk_gmac0_rgmii_adjust(mac->hw,
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- state->interface,
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- state->speed);
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+ state->interface);
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/* mt7623_pad_clk_setup */
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for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
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@@ -4288,13 +4260,19 @@ static int mtk_add_mac(struct mtk_eth *e
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mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
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MAC_10 | MAC_100 | MAC_1000 | MAC_2500FD;
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- __set_bit(PHY_INTERFACE_MODE_MII,
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- mac->phylink_config.supported_interfaces);
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- __set_bit(PHY_INTERFACE_MODE_GMII,
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- mac->phylink_config.supported_interfaces);
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+ /* MT7623 gmac0 is now missing its speed-specific PLL configuration
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+ * in its .mac_config method (since state->speed is not valid there.
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+ * Disable support for MII, GMII and RGMII.
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+ */
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+ if (!mac->hw->soc->disable_pll_modes || mac->id != 0) {
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+ __set_bit(PHY_INTERFACE_MODE_MII,
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+ mac->phylink_config.supported_interfaces);
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+ __set_bit(PHY_INTERFACE_MODE_GMII,
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+ mac->phylink_config.supported_interfaces);
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- if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII))
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- phy_interface_set_rgmii(mac->phylink_config.supported_interfaces);
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+ if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII))
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+ phy_interface_set_rgmii(mac->phylink_config.supported_interfaces);
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+ }
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if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII) && !mac->id)
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__set_bit(PHY_INTERFACE_MODE_TRGMII,
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@@ -4754,6 +4732,7 @@ static const struct mtk_soc_data mt7623_
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.offload_version = 1,
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.hash_offset = 2,
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.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
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+ .disable_pll_modes = true,
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.txrx = {
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.txd_size = sizeof(struct mtk_tx_dma),
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.rxd_size = sizeof(struct mtk_rx_dma),
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--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
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+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
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@@ -1027,6 +1027,7 @@ struct mtk_soc_data {
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u16 foe_entry_size;
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netdev_features_t hw_features;
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bool has_accounting;
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+ bool disable_pll_modes;
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struct {
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u32 txd_size;
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u32 rxd_size;
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