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f2e1e156c0
This adds support for eBPF JIT for 32 bit targets and significantly improves correctness. Signed-off-by: Felix Fietkau <nbd@nbd.name>
32 lines
1.3 KiB
Diff
32 lines
1.3 KiB
Diff
From: Johan Almbladh <johan.almbladh@anyfinetworks.com>
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Date: Tue, 5 Oct 2021 18:54:03 +0200
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Subject: [PATCH] mips: uasm: Add workaround for Loongson-2F nop CPU errata
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This patch implements a workaround for the Loongson-2F nop in generated,
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code, if the existing option CONFIG_CPU_NOP_WORKAROUND is set. Before,
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the binutils option -mfix-loongson2f-nop was enabled, but no workaround
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was done when emitting MIPS code. Now, the nop pseudo instruction is
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emitted as "or ax,ax,zero" instead of the default "sll zero,zero,0". This
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is consistent with the workaround implemented by binutils.
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Link: https://sourceware.org/legacy-ml/binutils/2009-11/msg00387.html
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Signed-off-by: Johan Almbladh <johan.almbladh@anyfinetworks.com>
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Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
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---
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--- a/arch/mips/include/asm/uasm.h
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+++ b/arch/mips/include/asm/uasm.h
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@@ -249,7 +249,11 @@ static inline void uasm_l##lb(struct uas
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#define uasm_i_bnezl(buf, rs, off) uasm_i_bnel(buf, rs, 0, off)
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#define uasm_i_ehb(buf) uasm_i_sll(buf, 0, 0, 3)
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#define uasm_i_move(buf, a, b) UASM_i_ADDU(buf, a, 0, b)
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+#ifdef CONFIG_CPU_NOP_WORKAROUNDS
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+#define uasm_i_nop(buf) uasm_i_or(buf, 1, 1, 0)
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+#else
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#define uasm_i_nop(buf) uasm_i_sll(buf, 0, 0, 0)
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+#endif
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#define uasm_i_ssnop(buf) uasm_i_sll(buf, 0, 0, 1)
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static inline void uasm_i_drotr_safe(u32 **p, unsigned int a1,
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