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cddd459140
Add patches for linux-5.4. The patches are from NXP LSDK-20.04 release which was tagged LSDK-20.04-V5.4. https://source.codeaurora.org/external/qoriq/qoriq-components/linux/ For boards LS1021A-IOT, and Traverse-LS1043 which are not involved in LSDK, port the dts patches from 4.14. The patches are sorted into the following categories: 301-arch-xxxx 302-dts-xxxx 303-core-xxxx 701-net-xxxx 801-audio-xxxx 802-can-xxxx 803-clock-xxxx 804-crypto-xxxx 805-display-xxxx 806-dma-xxxx 807-gpio-xxxx 808-i2c-xxxx 809-jailhouse-xxxx 810-keys-xxxx 811-kvm-xxxx 812-pcie-xxxx 813-pm-xxxx 814-qe-xxxx 815-sata-xxxx 816-sdhc-xxxx 817-spi-xxxx 818-thermal-xxxx 819-uart-xxxx 820-usb-xxxx 821-vfio-xxxx Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
138 lines
4.8 KiB
Diff
138 lines
4.8 KiB
Diff
From b752c8ed4ab83d47a585c363056d64fb978ef481 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Horia=20Geant=C4=83?= <horia.geanta@nxp.com>
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Date: Fri, 27 Sep 2019 20:05:26 +0300
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Subject: [PATCH] MLKU-114-2 crypto: caam - SCU firmware support
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Some i.MX8 processors, e.g. i.MX8QM (QM, QP), i.MX8QX (QXP, DX) have a
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System Controller Firmware (SCFW) running on a dedicated Cortex-M core
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that provides power, clock, and resource management.
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caam driver needs to be aware of SCU f/w presence, since some things
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are done differently:
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1. clocks are under SCU f/w control and are turned on automatically
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2. there is no access to controller's register page (note however that
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some registers are aliased in job rings' register pages)
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It's worth mentioning that due to this, MCFGR[PS] cannot be read
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and driver assumes MCFGR[PS] = b'0 - engine using 32-bit address pointers.
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This is in sync with the limitation imposed by the
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SECO (Security Controller) ROM and f/w running on a dedicated Cortex-M.
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3. as a consequence of "2.", part of the initialization is moved in
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other f/w (SCU, TF-A etc.), e.g. RNG initialization
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Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
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---
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drivers/crypto/caam/ctrl.c | 28 ++++++++++++++++++++++++++--
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drivers/crypto/caam/intern.h | 1 +
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2 files changed, 27 insertions(+), 2 deletions(-)
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--- a/drivers/crypto/caam/ctrl.c
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+++ b/drivers/crypto/caam/ctrl.c
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@@ -596,6 +596,17 @@ static int caam_probe(struct platform_de
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caam_imx = (bool)imx_soc_match;
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if (imx_soc_match) {
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+ np = of_find_compatible_node(NULL, NULL, "fsl,imx-scu");
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+ ctrlpriv->scu_en = !!np;
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+ of_node_put(np);
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+
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+ /*
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+ * CAAM clocks cannot be controlled from kernel.
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+ * They are automatically turned on by SCU f/w.
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+ */
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+ if (ctrlpriv->scu_en)
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+ goto iomap_ctrl;
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+
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if (!imx_soc_match->data) {
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dev_err(dev, "No clock data provided for i.MX SoC");
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return -EINVAL;
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@@ -606,7 +617,7 @@ static int caam_probe(struct platform_de
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return ret;
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}
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-
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+iomap_ctrl:
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/* Get configuration properties from device tree */
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/* First, get register page */
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ctrl = devm_of_iomap(dev, nprop, 0, NULL);
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@@ -646,7 +657,8 @@ static int caam_probe(struct platform_de
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caam_little_end = !(bool)(rd_reg32(&perfmon->status) &
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(CSTA_PLEND | CSTA_ALT_PLEND));
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comp_params = rd_reg32(&perfmon->comp_parms_ms);
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- if (comp_params & CTPR_MS_PS && rd_reg32(&ctrl->mcr) & MCFGR_LONG_PTR)
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+ if (!ctrlpriv->scu_en && comp_params & CTPR_MS_PS &&
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+ rd_reg32(&ctrl->mcr) & MCFGR_LONG_PTR)
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caam_ptr_sz = sizeof(u64);
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else
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caam_ptr_sz = sizeof(u32);
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@@ -696,6 +708,9 @@ static int caam_probe(struct platform_de
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/* Get the IRQ of the controller (for security violations only) */
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ctrlpriv->secvio_irq = irq_of_parse_and_map(nprop, 0);
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+ if (ctrlpriv->scu_en)
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+ goto set_dma_mask;
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+
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/*
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* Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel,
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* long pointers in master configuration register.
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@@ -739,6 +754,7 @@ static int caam_probe(struct platform_de
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JRSTART_JR1_START | JRSTART_JR2_START |
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JRSTART_JR3_START);
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+set_dma_mask:
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ret = dma_set_mask_and_coherent(dev, caam_get_dma_mask(dev));
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if (ret) {
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dev_err(dev, "dma_set_mask_and_coherent failed (%d)\n", ret);
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@@ -785,6 +801,9 @@ static int caam_probe(struct platform_de
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return -ENOMEM;
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}
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+ if (ctrlpriv->scu_en)
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+ goto report_live;
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+
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if (ctrlpriv->era < 10) {
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rng_vid = (rd_reg32(&perfmon->cha_id_ls) &
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CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT;
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@@ -865,6 +884,7 @@ static int caam_probe(struct platform_de
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/* NOTE: RTIC detection ought to go here, around Si time */
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+report_live:
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caam_id = (u64)rd_reg32(&perfmon->caam_id_ms) << 32 |
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(u64)rd_reg32(&perfmon->caam_id_ls);
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@@ -908,6 +928,9 @@ static int caam_probe(struct platform_de
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ctrlpriv->ctl, &perfmon->status,
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&caam_fops_u32_ro);
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+ if (ctrlpriv->scu_en)
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+ goto probe_jrs;
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+
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/* Internal covering keys (useful in non-secure mode only) */
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ctrlpriv->ctl_kek_wrap.data = (__force void *)&ctrlpriv->ctrl->kek[0];
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ctrlpriv->ctl_kek_wrap.size = KEK_KEY_SIZE * sizeof(u32);
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@@ -925,6 +948,7 @@ static int caam_probe(struct platform_de
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&ctrlpriv->ctl_tdsk_wrap);
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#endif
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+probe_jrs:
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ret = devm_of_platform_populate(dev);
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if (ret)
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dev_err(dev, "JR platform devices creation error\n");
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--- a/drivers/crypto/caam/intern.h
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+++ b/drivers/crypto/caam/intern.h
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@@ -82,6 +82,7 @@ struct caam_drv_private {
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u8 total_jobrs; /* Total Job Rings in device */
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u8 qi_present; /* Nonzero if QI present in device */
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u8 mc_en; /* Nonzero if MC f/w is active */
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+ u8 scu_en; /* Nonzero if SCU f/w is active */
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int secvio_irq; /* Security violation interrupt number */
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int virt_en; /* Virtualization enabled in CAAM */
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int era; /* CAAM Era (internal HW revision) */
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