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8cacf2bda8
This series of upstream patches makes the system controller node as a reset provider[1][2], and it also includes some clock and reset driver fixes[3][4]. Meanwhile, all clocks and resets properties in the SoC device tree have been updated to be compatible with the new driver. [1] https://lore.kernel.org/r/20220110114930.1406665-2-sergio.paracuellos@gmail.com [2] https://lore.kernel.org/r/20220210094859.927868-2-sergio.paracuellos@gmail.com [3] https://lore.kernel.org/r/20221217074806.3225150-1-sergio.paracuellos@gmail.com [4] https://lore.kernel.org/r/20230206083305.147582-1-sergio.paracuellos@gmail.com Tested on RAISECOM MSG1500 X.00 Signed-off-by: John Thomson <git@johnthomson.fastmail.com.au> Signed-off-by: Shiji Yang <yangshiji66@qq.com>
78 lines
3.1 KiB
Diff
78 lines
3.1 KiB
Diff
From 35dcae535afc153fa83f2fe51c0812536c192c58 Mon Sep 17 00:00:00 2001
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From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
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Date: Mon, 6 Feb 2023 09:33:05 +0100
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Subject: [PATCH] clk: ralink: fix 'mt7621_gate_is_enabled()' function
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Compiling clock driver with CONFIG_UBSAN enabled shows the following trace:
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UBSAN: shift-out-of-bounds in drivers/clk/ralink/clk-mt7621.c:121:15
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shift exponent 131072 is too large for 32-bit type 'long unsigned int'
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CPU: 1 PID: 1 Comm: swapper/0 Not tainted 5.15.86 #0
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Stack : ...
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Call Trace:
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[<80009a58>] show_stack+0x38/0x118
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[<8045ce04>] dump_stack_lvl+0x60/0x80
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[<80458868>] ubsan_epilogue+0x10/0x54
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[<804590e0>] __ubsan_handle_shift_out_of_bounds+0x118/0x190
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[<804c9a10>] mt7621_gate_is_enabled+0x98/0xa0
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[<804bb774>] clk_core_is_enabled+0x34/0x90
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[<80aad73c>] clk_disable_unused_subtree+0x98/0x1e4
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[<80aad6d4>] clk_disable_unused_subtree+0x30/0x1e4
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[<80aad6d4>] clk_disable_unused_subtree+0x30/0x1e4
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[<80aad900>] clk_disable_unused+0x78/0x120
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[<80002030>] do_one_initcall+0x54/0x1f0
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[<80a922a4>] kernel_init_freeable+0x280/0x31c
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[<808047c4>] kernel_init+0x20/0x118
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[<80003e58>] ret_from_kernel_thread+0x14/0x1c
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Shifting a value (131032) larger than the type (32 bit unsigned integer)
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is undefined behaviour in C.
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The problem is in 'mt7621_gate_is_enabled()' function which is using the
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'BIT()' kernel macro with the bit index for the clock gate to check if the
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bit is set. When the clock gates structure is created driver is already
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setting 'bit_idx' using 'BIT()' macro, so we are wrongly applying an extra
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'BIT()' mask here. Removing it solve the problem and makes this function
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correct. However when clock gating is correctly working, the kernel starts
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disabling those clocks that are not requested. Some drivers for this SoC
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are older than this clock driver itself. So to avoid the kernel to disable
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clocks that have been enabled until now, we must apply 'CLK_IS_CRITICAL'
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flag on gates initialization code.
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Fixes: 48df7a26f470 ("clk: ralink: add clock driver for mt7621 SoC")
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Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
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Link: https://lore.kernel.org/r/20230206083305.147582-1-sergio.paracuellos@gmail.com
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Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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---
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drivers/clk/ralink/clk-mt7621.c | 10 ++++++++--
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1 file changed, 8 insertions(+), 2 deletions(-)
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--- a/drivers/clk/ralink/clk-mt7621.c
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+++ b/drivers/clk/ralink/clk-mt7621.c
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@@ -121,7 +121,7 @@ static int mt7621_gate_is_enabled(struct
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if (regmap_read(sysc, SYSC_REG_CLKCFG1, &val))
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return 0;
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- return val & BIT(clk_gate->bit_idx);
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+ return val & clk_gate->bit_idx;
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}
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static const struct clk_ops mt7621_gate_ops = {
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@@ -133,8 +133,14 @@ static const struct clk_ops mt7621_gate_
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static int mt7621_gate_ops_init(struct device *dev,
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struct mt7621_gate *sclk)
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{
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+ /*
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+ * There are drivers for this SoC that are older
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+ * than clock driver and are not prepared for the clock.
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+ * We don't want the kernel to disable anything so we
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+ * add CLK_IS_CRITICAL flag here.
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+ */
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struct clk_init_data init = {
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- .flags = CLK_SET_RATE_PARENT,
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+ .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
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.num_parents = 1,
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.parent_names = &sclk->parent_name,
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.ops = &mt7621_gate_ops,
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