mirror of
https://git.openwrt.org/openwrt/openwrt.git
synced 2024-11-20 07:24:36 +01:00
155 lines
4.8 KiB
Diff
155 lines
4.8 KiB
Diff
Index: linux-2.6.23.16/drivers/mmc/host/sdhci.c
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===================================================================
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--- linux-2.6.23.16.orig/drivers/mmc/host/sdhci.c 2008-04-28 08:33:14.000000000 +0200
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+++ linux-2.6.23.16/drivers/mmc/host/sdhci.c 2008-04-28 08:36:40.000000000 +0200
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@@ -487,16 +487,16 @@
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* Controller doesn't count down when in single block mode.
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*/
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if (data->blocks == 1)
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- blocks = (data->error == MMC_ERR_NONE) ? 0 : 1;
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+ blocks = (data->error == 0) ? 0 : 1;
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else
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blocks = readw(host->ioaddr + SDHCI_BLOCK_COUNT);
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data->bytes_xfered = data->blksz * (data->blocks - blocks);
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- if ((data->error == MMC_ERR_NONE) && blocks) {
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+ if (!data->error && blocks) {
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printk(KERN_ERR "%s: Controller signalled completion even "
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"though there were blocks left.\n",
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mmc_hostname(host->mmc));
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- data->error = MMC_ERR_FAILED;
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+ data->error = -EIO;
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}
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if (data->stop) {
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@@ -504,7 +504,7 @@
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* The controller needs a reset of internal state machines
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* upon error conditions.
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*/
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- if (data->error != MMC_ERR_NONE) {
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+ if (data->error) {
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sdhci_reset(host, SDHCI_RESET_CMD);
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sdhci_reset(host, SDHCI_RESET_DATA);
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}
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@@ -539,7 +539,7 @@
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printk(KERN_ERR "%s: Controller never released "
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"inhibit bit(s).\n", mmc_hostname(host->mmc));
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sdhci_dumpregs(host);
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- cmd->error = MMC_ERR_FAILED;
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+ cmd->error = -EIO;
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tasklet_schedule(&host->finish_tasklet);
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return;
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}
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@@ -560,7 +560,7 @@
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if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
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printk(KERN_ERR "%s: Unsupported response type!\n",
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mmc_hostname(host->mmc));
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- cmd->error = MMC_ERR_INVALID;
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+ cmd->error = -EINVAL;
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tasklet_schedule(&host->finish_tasklet);
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return;
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}
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@@ -607,7 +607,7 @@
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}
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}
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- host->cmd->error = MMC_ERR_NONE;
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+ host->cmd->error = 0;
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if (host->data && host->data_early)
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sdhci_finish_data(host);
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@@ -730,7 +730,7 @@
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host->mrq = mrq;
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if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
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- host->mrq->cmd->error = MMC_ERR_TIMEOUT;
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+ host->mrq->cmd->error = -ENOMEDIUM;
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tasklet_schedule(&host->finish_tasklet);
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} else
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sdhci_send_command(host, mrq->cmd);
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@@ -839,7 +839,7 @@
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sdhci_reset(host, SDHCI_RESET_CMD);
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sdhci_reset(host, SDHCI_RESET_DATA);
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- host->mrq->cmd->error = MMC_ERR_FAILED;
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+ host->mrq->cmd->error = -ENOMEDIUM;
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tasklet_schedule(&host->finish_tasklet);
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}
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}
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@@ -867,9 +867,9 @@
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* The controller needs a reset of internal state machines
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* upon error conditions.
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*/
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- if ((mrq->cmd->error != MMC_ERR_NONE) ||
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- (mrq->data && ((mrq->data->error != MMC_ERR_NONE) ||
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- (mrq->data->stop && (mrq->data->stop->error != MMC_ERR_NONE))))) {
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+ if (mrq->cmd->error ||
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+ (mrq->data && (mrq->data->error ||
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+ (mrq->data->stop && mrq->data->stop->error)))) {
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/* Some controllers need this kick or reset won't work here */
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if (host->chip->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
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@@ -914,13 +914,13 @@
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sdhci_dumpregs(host);
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if (host->data) {
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- host->data->error = MMC_ERR_TIMEOUT;
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+ host->data->error = -ETIMEDOUT;
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sdhci_finish_data(host);
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} else {
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if (host->cmd)
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- host->cmd->error = MMC_ERR_TIMEOUT;
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+ host->cmd->error = -ETIMEDOUT;
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else
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- host->mrq->cmd->error = MMC_ERR_TIMEOUT;
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+ host->mrq->cmd->error = -ETIMEDOUT;
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tasklet_schedule(&host->finish_tasklet);
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}
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@@ -949,13 +949,12 @@
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}
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if (intmask & SDHCI_INT_TIMEOUT)
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- host->cmd->error = MMC_ERR_TIMEOUT;
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- else if (intmask & SDHCI_INT_CRC)
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- host->cmd->error = MMC_ERR_BADCRC;
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- else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX))
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- host->cmd->error = MMC_ERR_FAILED;
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+ host->cmd->error = -ETIMEDOUT;
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+ else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
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+ SDHCI_INT_INDEX))
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+ host->cmd->error = -EILSEQ;
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- if (host->cmd->error != MMC_ERR_NONE)
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+ if (host->cmd->error)
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tasklet_schedule(&host->finish_tasklet);
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else if (intmask & SDHCI_INT_RESPONSE)
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sdhci_finish_command(host);
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@@ -982,13 +981,11 @@
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}
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if (intmask & SDHCI_INT_DATA_TIMEOUT)
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- host->data->error = MMC_ERR_TIMEOUT;
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- else if (intmask & SDHCI_INT_DATA_CRC)
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- host->data->error = MMC_ERR_BADCRC;
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- else if (intmask & SDHCI_INT_DATA_END_BIT)
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- host->data->error = MMC_ERR_FAILED;
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+ host->data->error = -ETIMEDOUT;
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+ else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
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+ host->data->error = -EILSEQ;
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- if (host->data->error != MMC_ERR_NONE)
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+ if (host->data->error)
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sdhci_finish_data(host);
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else {
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if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
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@@ -1320,7 +1317,7 @@
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mmc->ops = &sdhci_ops;
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mmc->f_min = host->max_clk / 256;
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mmc->f_max = host->max_clk;
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- mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE | MMC_CAP_BYTEBLOCK;
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+ mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE;
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if (caps & SDHCI_CAN_DO_HISPD)
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mmc->caps |= MMC_CAP_SD_HIGHSPEED;
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