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Qualcomm Atheros IPQ807x is a modern WiSoC featuring: * Quad Core ARMv8 Cortex A-53 * @ 2.2 GHz (IPQ8072A/4A/6A/8A) Codename Hawkeye * @ 1.4 GHz (IPQ8070A/1A) Codename Acorn * Dual Band simultaneaous IEEE 802.11ax * 5G: 8x8/80 or 4x4/160MHz (IPQ8074A/8A) * 5G: 4x4/80 or 2x2/160MHz (IPQ8071A/2A/6A) * 5G: 2x2/80MHz (IPQ8070A) * 2G: 4x4/40MHz (IPQ8072A/4A/6A/8A) * 2G: 2x2/40MHz (IPQ8070A/1A) * 1x PSGMII via QCA8072/5 (Max 5x 1GbE ports) * 2x SGMII/USXGMII (1/2.5/5/10 GbE) on Hawkeye * 2x SGMII/USXGMII (1/2.5/5 GbE) on Acorn * DDR3L/4 32/16 bit up to 2400MT/s * SDIO 3.0/SD card 3.0/eMMC 5.1 * Dual USB 3.0 * One PCIe Gen2.1 and one PCIe Gen3.0 port (Single lane) * Parallel NAND (ONFI)/LCD * 6x QUP BLSP SPI/I2C/UART * I2S, PCM, and TDMA * HW PWM * 1.8V configurable GPIO * Companion PMP8074 PMIC via SPMI (GPIOS, RTC etc) Note that only v2 SOC models aka the ones ending with A suffix are supported, v1 models do not comply to the final 802.11ax and have lower clocks, lack the Gen3 PCIe etc. SoC itself has two UBI32 cores for the NSS offloading system, however currently no offloading is supported. Signed-off-by: Robert Marko <robimarko@gmail.com>
39 lines
1.4 KiB
Diff
39 lines
1.4 KiB
Diff
From 614d31c231c7707322b643f409eeb7e28adc7f8c Mon Sep 17 00:00:00 2001
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From: Robert Marko <robimarko@gmail.com>
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Date: Sun, 8 Jan 2023 13:36:28 +0100
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Subject: [PATCH] clk: qcom: ipq8074: populate fw_name for usb3phy-s
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Having only .name populated in parent_data for clocks which are only
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globally searchable currently will not work as the clk core won't copy
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that name if there is no .fw_name present as well.
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So, populate .fw_name for usb3phy clocks in parent_data as they were
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missed by me in ("clk: qcom: ipq8074: populate fw_name for all parents").
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Fixes: ae55ad32e273 ("clk: qcom: ipq8074: convert to parent data")
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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---
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drivers/clk/qcom/gcc-ipq8074.c | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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--- a/drivers/clk/qcom/gcc-ipq8074.c
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+++ b/drivers/clk/qcom/gcc-ipq8074.c
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@@ -934,7 +934,7 @@ static struct clk_rcg2 usb0_mock_utmi_cl
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};
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static const struct clk_parent_data gcc_usb3phy_0_cc_pipe_clk_xo[] = {
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- { .name = "usb3phy_0_cc_pipe_clk" },
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+ { .fw_name = "usb3phy_0_cc_pipe_clk", .name = "usb3phy_0_cc_pipe_clk" },
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{ .fw_name = "xo", .name = "xo" },
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};
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@@ -1002,7 +1002,7 @@ static struct clk_rcg2 usb1_mock_utmi_cl
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};
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static const struct clk_parent_data gcc_usb3phy_1_cc_pipe_clk_xo[] = {
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- { .name = "usb3phy_1_cc_pipe_clk" },
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+ { .fw_name = "usb3phy_1_cc_pipe_clk", .name = "usb3phy_1_cc_pipe_clk" },
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{ .fw_name = "xo", .name = "xo" },
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};
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