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Qualcomm Atheros IPQ807x is a modern WiSoC featuring: * Quad Core ARMv8 Cortex A-53 * @ 2.2 GHz (IPQ8072A/4A/6A/8A) Codename Hawkeye * @ 1.4 GHz (IPQ8070A/1A) Codename Acorn * Dual Band simultaneaous IEEE 802.11ax * 5G: 8x8/80 or 4x4/160MHz (IPQ8074A/8A) * 5G: 4x4/80 or 2x2/160MHz (IPQ8071A/2A/6A) * 5G: 2x2/80MHz (IPQ8070A) * 2G: 4x4/40MHz (IPQ8072A/4A/6A/8A) * 2G: 2x2/40MHz (IPQ8070A/1A) * 1x PSGMII via QCA8072/5 (Max 5x 1GbE ports) * 2x SGMII/USXGMII (1/2.5/5/10 GbE) on Hawkeye * 2x SGMII/USXGMII (1/2.5/5 GbE) on Acorn * DDR3L/4 32/16 bit up to 2400MT/s * SDIO 3.0/SD card 3.0/eMMC 5.1 * Dual USB 3.0 * One PCIe Gen2.1 and one PCIe Gen3.0 port (Single lane) * Parallel NAND (ONFI)/LCD * 6x QUP BLSP SPI/I2C/UART * I2S, PCM, and TDMA * HW PWM * 1.8V configurable GPIO * Companion PMP8074 PMIC via SPMI (GPIOS, RTC etc) Note that only v2 SOC models aka the ones ending with A suffix are supported, v1 models do not comply to the final 802.11ax and have lower clocks, lack the Gen3 PCIe etc. SoC itself has two UBI32 cores for the NSS offloading system, however currently no offloading is supported. Signed-off-by: Robert Marko <robimarko@gmail.com>
55 lines
1.9 KiB
Diff
55 lines
1.9 KiB
Diff
From 72bc31aa621e21a7c36a7da8aa6f6a77bb234e0b Mon Sep 17 00:00:00 2001
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From: Stephan Gerhold <stephan.gerhold@kernkonzept.com>
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Date: Wed, 6 Jul 2022 15:41:29 +0200
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Subject: [PATCH] clk: qcom: reset: Allow specifying custom reset delay
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The amount of time required between asserting and deasserting the reset
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signal can vary depending on the involved hardware component. Sometimes
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1 us might not be enough and a larger delay is necessary to conform to
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the specifications.
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Usually this is worked around in the consuming drivers, by replacing
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reset_control_reset() with a sequence of reset_control_assert(), waiting
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for a custom delay, followed by reset_control_deassert().
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However, in some cases the driver making use of the reset is generic and
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can be used with different reset controllers. In this case the reset
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time requirement is better handled directly by the reset controller
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driver.
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Make this possible by adding an "udelay" field to the qcom_reset_map
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that allows setting a different reset delay (in microseconds).
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Signed-off-by: Stephan Gerhold <stephan.gerhold@kernkonzept.com>
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Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Link: https://lore.kernel.org/r/20220706134132.3623415-4-stephan.gerhold@kernkonzept.com
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---
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drivers/clk/qcom/reset.c | 4 +++-
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drivers/clk/qcom/reset.h | 1 +
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2 files changed, 4 insertions(+), 1 deletion(-)
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--- a/drivers/clk/qcom/reset.c
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+++ b/drivers/clk/qcom/reset.c
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@@ -13,8 +13,10 @@
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static int qcom_reset(struct reset_controller_dev *rcdev, unsigned long id)
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{
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+ struct qcom_reset_controller *rst = to_qcom_reset_controller(rcdev);
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+
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rcdev->ops->assert(rcdev, id);
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- udelay(1);
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+ udelay(rst->reset_map[id].udelay ?: 1); /* use 1 us as default */
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rcdev->ops->deassert(rcdev, id);
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return 0;
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}
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--- a/drivers/clk/qcom/reset.h
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+++ b/drivers/clk/qcom/reset.h
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@@ -11,6 +11,7 @@
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struct qcom_reset_map {
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unsigned int reg;
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u8 bit;
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+ u8 udelay;
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};
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struct regmap;
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