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Qualcomm Atheros IPQ807x is a modern WiSoC featuring: * Quad Core ARMv8 Cortex A-53 * @ 2.2 GHz (IPQ8072A/4A/6A/8A) Codename Hawkeye * @ 1.4 GHz (IPQ8070A/1A) Codename Acorn * Dual Band simultaneaous IEEE 802.11ax * 5G: 8x8/80 or 4x4/160MHz (IPQ8074A/8A) * 5G: 4x4/80 or 2x2/160MHz (IPQ8071A/2A/6A) * 5G: 2x2/80MHz (IPQ8070A) * 2G: 4x4/40MHz (IPQ8072A/4A/6A/8A) * 2G: 2x2/40MHz (IPQ8070A/1A) * 1x PSGMII via QCA8072/5 (Max 5x 1GbE ports) * 2x SGMII/USXGMII (1/2.5/5/10 GbE) on Hawkeye * 2x SGMII/USXGMII (1/2.5/5 GbE) on Acorn * DDR3L/4 32/16 bit up to 2400MT/s * SDIO 3.0/SD card 3.0/eMMC 5.1 * Dual USB 3.0 * One PCIe Gen2.1 and one PCIe Gen3.0 port (Single lane) * Parallel NAND (ONFI)/LCD * 6x QUP BLSP SPI/I2C/UART * I2S, PCM, and TDMA * HW PWM * 1.8V configurable GPIO * Companion PMP8074 PMIC via SPMI (GPIOS, RTC etc) Note that only v2 SOC models aka the ones ending with A suffix are supported, v1 models do not comply to the final 802.11ax and have lower clocks, lack the Gen3 PCIe etc. SoC itself has two UBI32 cores for the NSS offloading system, however currently no offloading is supported. Signed-off-by: Robert Marko <robimarko@gmail.com>
64 lines
2.2 KiB
Diff
64 lines
2.2 KiB
Diff
From 6b9d5ecd2913758780a0529f9b95392f330b721b Mon Sep 17 00:00:00 2001
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From: Robert Marko <robimarko@gmail.com>
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Date: Fri, 19 Aug 2022 00:06:21 +0200
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Subject: [PATCH] clk: qcom: apss-ipq6018: fix apcs_alias0_clk_src
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While working on IPQ8074 APSS driver it was discovered that IPQ6018 and
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IPQ8074 use almost the same PLL and APSS clocks, however APSS driver is
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currently broken.
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More precisely apcs_alias0_clk_src is broken, it was added as regmap_mux
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clock.
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However after debugging why it was always stuck at 800Mhz, it was figured
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out that its not regmap_mux compatible at all.
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It is a simple mux but it uses RCG2 register layout and control bits, so
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utilize the new clk_rcg2_mux_closest_ops to correctly drive it while not
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having to provide a dummy frequency table.
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While we are here, use ARRAY_SIZE for number of parents.
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Tested on IPQ6018-CP01-C1 reference board and multiple IPQ8074 boards.
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Fixes: 5e77b4ef1b19 ("clk: qcom: Add ipq6018 apss clock controller")
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Link: https://lore.kernel.org/r/20220818220628.339366-2-robimarko@gmail.com
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---
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drivers/clk/qcom/apss-ipq6018.c | 13 ++++++-------
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1 file changed, 6 insertions(+), 7 deletions(-)
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--- a/drivers/clk/qcom/apss-ipq6018.c
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+++ b/drivers/clk/qcom/apss-ipq6018.c
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@@ -16,7 +16,7 @@
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#include "clk-regmap.h"
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#include "clk-branch.h"
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#include "clk-alpha-pll.h"
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-#include "clk-regmap-mux.h"
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+#include "clk-rcg.h"
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enum {
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P_XO,
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@@ -33,16 +33,15 @@ static const struct parent_map parents_a
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{ P_APSS_PLL_EARLY, 5 },
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};
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-static struct clk_regmap_mux apcs_alias0_clk_src = {
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- .reg = 0x0050,
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- .width = 3,
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- .shift = 7,
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+static struct clk_rcg2 apcs_alias0_clk_src = {
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+ .cmd_rcgr = 0x0050,
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+ .hid_width = 5,
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.parent_map = parents_apcs_alias0_clk_src_map,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "apcs_alias0_clk_src",
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.parent_data = parents_apcs_alias0_clk_src,
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- .num_parents = 2,
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- .ops = &clk_regmap_mux_closest_ops,
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+ .num_parents = ARRAY_SIZE(parents_apcs_alias0_clk_src),
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+ .ops = &clk_rcg2_mux_closest_ops,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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