Mathias Kresin bc04cf780e ath79: ar724x: fix pll settings ... Add the syscon compatible, otherwise used functions like syscon_regmap_lookup_by_phandle() will return an error and setting the ethernet pll data wont work at all. Fix the pll register width. Writing to registers out of the range via syscon isn't possible and returns an error. On ar7242 the last pll register - Current Audio Modulation Logic Output - is at 0x1805003c. Signed-off-by: Mathias Kresin <dev@kresin.me>		2018-05-17 07:40:19 +02:00
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imagebuilder	imagebuilder: remove split patch dirs from imagebuilder archive	2018-03-07 09:59:08 +01:00
linux	ath79: ar724x: fix pll settings	2018-05-17 07:40:19 +02:00
sdk	sdk: change base feed fallback to git.openwrt.org	2018-01-11 18:20:07 +01:00
toolchain	merge: etc: update remaining files	2017-12-08 19:41:18 +01:00
Config.in	config: set ARCH if powerpc64 is selected in the configuration	2017-10-24 13:24:04 +02:00
Makefile