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Deleted (upstreamed): bcm27xx/patches-5.10/950-0669-drm-vc4-hdmi-Make-sure-the-device-is-powered-with-CE.patch [1] bcm27xx/patches-5.10/950-0672-drm-vc4-hdmi-Move-initial-register-read-after-pm_run.patch [1] gemini/patches-5.10/0003-ARM-dts-gemini-NAS4220-B-fis-index-block-with-128-Ki.patch [2] Manually rebased: bcm27xx/patches-5.10/950-0675-drm-vc4-hdmi-Drop-devm-interrupt-handler-for-CEC-int.patch Manually reverted: generic/pending-5.10/860-Revert-ASoC-mediatek-Check-for-error-clk-pointer.patch [3] [1] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.10.94&id=55b10b88ac8654fc2f31518aa349a2e643b37f18 [2] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.10.94&id=958a8819d41420d7a74ed922a09cacc0ba3a4218 [3] https://lore.kernel.org/all/trinity-2a727d96-0335-4d03-8f30-e22a0e10112d-1643363480085@3c-app-gmx-bap33/ Signed-off-by: Rui Salvaterra <rsalvaterra@gmail.com> Signed-off-by: Daniel Golle <daniel@makrotopia.org>
63 lines
2.1 KiB
Diff
63 lines
2.1 KiB
Diff
From 4ec54ed688271966193b572ba5b150c6a4d270fc Mon Sep 17 00:00:00 2001
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From: Tim Gover <tim.gover@raspberrypi.com>
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Date: Thu, 24 Jun 2021 17:58:05 +0100
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Subject: [PATCH] drm: vc4: Fix pixel-wrap issue with DVP teardown
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Adjust the DVP enable/disable sequence to avoid a pixel getting stuck
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in an internal, non resettable FIFO within PixelValve when changing
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HDMI resolution.
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The blank pixels features of the DVP can prevent signals back to
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pixelvalve causing it to not clear the FIFO. Adjust the ordering
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and timing of operations to ensure the clear signal makes it through to
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pixelvalve.
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Signed-off-by: Tim Gover <tim.gover@raspberrypi.com>
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---
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drivers/gpu/drm/vc4/vc4_hdmi.c | 15 ++++++++-------
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1 file changed, 8 insertions(+), 7 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
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+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
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@@ -611,12 +611,12 @@ static void vc4_hdmi_encoder_post_crtc_d
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HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0);
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- HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) |
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- VC4_HD_VID_CTL_CLRRGB | VC4_HD_VID_CTL_CLRSYNC);
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+ HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB);
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- HDMI_WRITE(HDMI_VID_CTL,
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- HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);
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+ mdelay(1);
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+ HDMI_WRITE(HDMI_VID_CTL,
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+ HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
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vc4_hdmi_disable_scrambling(encoder);
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}
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@@ -626,12 +626,12 @@ static void vc4_hdmi_encoder_post_crtc_p
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struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
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int ret;
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+ HDMI_WRITE(HDMI_VID_CTL,
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+ HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);
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+
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if (vc4_hdmi->variant->phy_disable)
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vc4_hdmi->variant->phy_disable(vc4_hdmi);
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- HDMI_WRITE(HDMI_VID_CTL,
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- HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
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-
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clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);
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if (vc4_hdmi->bvb_req)
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clk_request_done(vc4_hdmi->bvb_req);
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@@ -1011,6 +1011,7 @@ static void vc4_hdmi_encoder_post_crtc_e
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HDMI_WRITE(HDMI_VID_CTL,
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VC4_HD_VID_CTL_ENABLE |
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+ VC4_HD_VID_CTL_CLRRGB |
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VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
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VC4_HD_VID_CTL_FRAME_COUNTER_RESET |
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(vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
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