mirror of
https://git.openwrt.org/openwrt/openwrt.git
synced 2024-05-23 07:56:18 +02:00
9226f1e419
Endianness depends on CPU architecture. CONFIG_CPU_(BIG/LITTLE)_ENDIAN should be enabled on target or subtarget based on SoC architecture. Fixes warning: $ make kernel_oldconfig CONFIG_TARGET=subtarget ... .config:1008:warning: override: CPU_LITTLE_ENDIAN changes choice state .... Summary: - ARC - only the CONFIG_CPU_BIG_ENDIAN symbol is defined for this architeture. If it is disabled then the processor operates in LITTLE_ENDIAN mode (default), - ARM32 - CONFIG_CPU_LITTLE_ENDIAN symbol available since kernel 5.19. This option should be enabled after OpenWRT moves to kernel 6.x. After refreshing the kernel, the symbol disappears, - ARM64 - enabled CONFIG_CPU_LITTLE_ENDIAN, - MIPS - enabled relevant symbols, - POWERPC - enabled CONFIG_CPU_BIG_ENDIAN, - UML - Symbols are not defined for this architecture, - X86 - always little endian. Symbols are not defined for this architecture. Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
183 lines
4.6 KiB
Plaintext
183 lines
4.6 KiB
Plaintext
CONFIG_ARCH_32BIT_OFF_T=y
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CONFIG_ARCH_HIBERNATION_POSSIBLE=y
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CONFIG_ARCH_KEEP_MEMBLOCK=y
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CONFIG_ARCH_MMAP_RND_BITS_MAX=15
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CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
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CONFIG_ARCH_SUSPEND_POSSIBLE=y
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CONFIG_BLK_MQ_PCI=y
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CONFIG_CEVT_R4K=y
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CONFIG_CLONE_BACKWARDS=y
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CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
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CONFIG_CMDLINE_BOOL=y
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# CONFIG_CMDLINE_OVERRIDE is not set
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CONFIG_COMMON_CLK=y
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CONFIG_COMPAT_32BIT_TIME=y
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CONFIG_CPU_GENERIC_DUMP_TLB=y
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CONFIG_CPU_HAS_DIEI=y
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CONFIG_CPU_HAS_PREFETCH=y
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CONFIG_CPU_HAS_RIXI=y
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CONFIG_CPU_HAS_SYNC=y
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CONFIG_CPU_LITTLE_ENDIAN=y
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CONFIG_CPU_MIPS32=y
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# CONFIG_CPU_MIPS32_R1 is not set
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CONFIG_CPU_MIPS32_R2=y
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CONFIG_CPU_MIPSR2=y
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CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
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CONFIG_CPU_R4K_CACHE_TLB=y
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CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
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CONFIG_CPU_SUPPORTS_HIGHMEM=y
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CONFIG_CPU_SUPPORTS_MSA=y
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CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
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CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
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CONFIG_CRYPTO_RNG2=y
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CONFIG_CSRC_R4K=y
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CONFIG_DMA_NONCOHERENT=y
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# CONFIG_DTB_RT2880_EVAL is not set
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CONFIG_DTB_RT_NONE=y
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CONFIG_DTC=y
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CONFIG_EARLY_PRINTK=y
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CONFIG_FIXED_PHY=y
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CONFIG_FWNODE_MDIO=y
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CONFIG_FW_LOADER_PAGED_BUF=y
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CONFIG_GENERIC_ALLOCATOR=y
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CONFIG_GENERIC_ATOMIC64=y
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CONFIG_GENERIC_CLOCKEVENTS=y
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CONFIG_GENERIC_CMOS_UPDATE=y
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CONFIG_GENERIC_CPU_AUTOPROBE=y
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CONFIG_GENERIC_FIND_FIRST_BIT=y
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CONFIG_GENERIC_GETTIMEOFDAY=y
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CONFIG_GENERIC_IOMAP=y
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CONFIG_GENERIC_IRQ_CHIP=y
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CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
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CONFIG_GENERIC_IRQ_SHOW=y
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CONFIG_GENERIC_LIB_ASHLDI3=y
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CONFIG_GENERIC_LIB_ASHRDI3=y
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CONFIG_GENERIC_LIB_CMPDI2=y
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CONFIG_GENERIC_LIB_LSHRDI3=y
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CONFIG_GENERIC_LIB_UCMPDI2=y
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CONFIG_GENERIC_PCI_IOMAP=y
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CONFIG_GENERIC_PINCONF=y
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CONFIG_GENERIC_SCHED_CLOCK=y
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CONFIG_GENERIC_SMP_IDLE_THREAD=y
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CONFIG_GENERIC_TIME_VSYSCALL=y
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CONFIG_GPIO_CDEV=y
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CONFIG_GPIO_RALINK=y
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CONFIG_HANDLE_DOMAIN_IRQ=y
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CONFIG_HARDWARE_WATCHPOINTS=y
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CONFIG_HAS_DMA=y
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CONFIG_HAS_IOMEM=y
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CONFIG_HAS_IOPORT_MAP=y
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CONFIG_HZ_PERIODIC=y
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CONFIG_INITRAMFS_SOURCE=""
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CONFIG_IP17XX_PHY=y
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CONFIG_IRQCHIP=y
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CONFIG_IRQ_DOMAIN=y
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CONFIG_IRQ_FORCED_THREADING=y
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CONFIG_IRQ_INTC=y
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CONFIG_IRQ_MIPS_CPU=y
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CONFIG_IRQ_WORK=y
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CONFIG_LIBFDT=y
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CONFIG_LOCK_DEBUGGING_SUPPORT=y
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CONFIG_MDIO_BUS=y
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CONFIG_MDIO_DEVICE=y
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CONFIG_MDIO_DEVRES=y
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CONFIG_MEMFD_CREATE=y
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CONFIG_MIGRATION=y
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CONFIG_MIPS=y
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CONFIG_MIPS_ASID_BITS=8
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CONFIG_MIPS_ASID_SHIFT=0
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CONFIG_MIPS_AUTO_PFN_OFFSET=y
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CONFIG_MIPS_CLOCK_VSYSCALL=y
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# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set
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# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set
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CONFIG_MIPS_CMDLINE_FROM_DTB=y
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CONFIG_MIPS_EBPF_JIT=y
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CONFIG_MIPS_L1_CACHE_SHIFT=4
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CONFIG_MIPS_L1_CACHE_SHIFT_4=y
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CONFIG_MIPS_LD_CAN_LINK_VDSO=y
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# CONFIG_MIPS_NO_APPENDED_DTB is not set
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CONFIG_MIPS_RAW_APPENDED_DTB=y
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CONFIG_MIPS_SPRAM=y
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CONFIG_MODULES_USE_ELF_REL=y
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# CONFIG_MTD_CFI_INTELEXT is not set
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CONFIG_MTD_CMDLINE_PARTS=y
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CONFIG_MTD_PHYSMAP=y
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CONFIG_MTD_SPI_NOR=y
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CONFIG_MTD_SPLIT_LZMA_FW=y
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CONFIG_MTD_SPLIT_UIMAGE_FW=y
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CONFIG_MTD_SPLIT_WRGG_FW=y
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CONFIG_NEED_DMA_MAP_STATE=y
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CONFIG_NEED_PER_CPU_KM=y
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CONFIG_NET_RALINK_MDIO=y
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CONFIG_NET_RALINK_MDIO_RT2880=y
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CONFIG_NET_RALINK_RT2880=y
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CONFIG_NET_RALINK_SOC=y
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CONFIG_NET_SELFTESTS=y
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CONFIG_NET_VENDOR_RALINK=y
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CONFIG_NLS=m
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CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
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CONFIG_NVMEM=y
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CONFIG_OF=y
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CONFIG_OF_ADDRESS=y
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CONFIG_OF_EARLY_FLATTREE=y
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CONFIG_OF_FLATTREE=y
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CONFIG_OF_GPIO=y
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CONFIG_OF_IRQ=y
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CONFIG_OF_KOBJ=y
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CONFIG_OF_MDIO=y
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CONFIG_PCI=y
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CONFIG_PCI_DOMAINS=y
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CONFIG_PCI_DRIVERS_LEGACY=y
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CONFIG_PERF_USE_VMALLOC=y
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CONFIG_PGTABLE_LEVELS=2
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CONFIG_PHYLIB=y
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# CONFIG_PHY_MT7621_PCI is not set
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# CONFIG_PHY_RALINK_USB is not set
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CONFIG_PINCTRL=y
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# CONFIG_PINCTRL_AW9523 is not set
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CONFIG_PINCTRL_RALINK=y
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CONFIG_PINCTRL_RT288X=y
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# CONFIG_PINCTRL_SINGLE is not set
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CONFIG_PTP_1588_CLOCK_OPTIONAL=y
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CONFIG_RALINK=y
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CONFIG_RALINK_WDT=y
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CONFIG_RATIONAL=y
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CONFIG_RESET_CONTROLLER=y
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CONFIG_SERIAL_8250_RT288X=y
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CONFIG_SERIAL_MCTRL_GPIO=y
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CONFIG_SERIAL_OF_PLATFORM=y
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# CONFIG_SOC_MT7620 is not set
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# CONFIG_SOC_MT7621 is not set
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CONFIG_SOC_RT288X=y
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# CONFIG_SOC_RT305X is not set
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# CONFIG_SOC_RT3883 is not set
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CONFIG_SPI=y
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CONFIG_SPI_MASTER=y
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CONFIG_SPI_MEM=y
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# CONFIG_SPI_MT7621 is not set
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CONFIG_SPI_RT2880=y
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CONFIG_SRCU=y
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CONFIG_SWCONFIG=y
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CONFIG_SWPHY=y
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CONFIG_SYSCTL_EXCEPTION_TRACE=y
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CONFIG_SYS_HAS_CPU_MIPS32_R1=y
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CONFIG_SYS_HAS_CPU_MIPS32_R2=y
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CONFIG_SYS_HAS_EARLY_PRINTK=y
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CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
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CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
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CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
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CONFIG_SYS_SUPPORTS_MIPS16=y
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CONFIG_SYS_SUPPORTS_ZBOOT=y
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CONFIG_TARGET_ISA_REV=2
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CONFIG_TICK_CPU_ACCOUNTING=y
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CONFIG_TINY_SRCU=y
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CONFIG_USB=m
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CONFIG_USB_COMMON=m
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CONFIG_USB_EHCI_HCD=m
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CONFIG_USB_EHCI_HCD_PLATFORM=m
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CONFIG_USB_OHCI_HCD=m
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CONFIG_USB_OHCI_HCD_PLATFORM=m
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CONFIG_USB_SUPPORT=y
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CONFIG_USE_OF=y
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CONFIG_WATCHDOG_CORE=y
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