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123 lines
3.1 KiB
C
123 lines
3.1 KiB
C
/*
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***************************************************************************
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* Definitions for IDT RC323434 CPU.
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*
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****************************************************************************
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* Kiran Rao
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*
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* Original form
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****************************************************************************
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* P. Sadik Oct 08, 2003
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*
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* Started revision history
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* Made IDT_BUS_FREQ a kernel configuration parameter
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****************************************************************************
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* P. Sadik Oct 10, 2003
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*
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* Removed IDT_BUS_FREQ, since this parameter is no longer required. Instead
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* idt_cpu_freq is used everywhere
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****************************************************************************
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* P. Sadik Oct 20, 2003
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*
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* Removed RC32434_BASE_BAUD
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****************************************************************************
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*/
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#ifndef _RC32434_H_
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#define _RC32434_H_
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#include <linux/autoconf.h>
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#include <linux/delay.h>
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#include <asm/io.h>
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#define RC32434_REG_BASE 0x18000000
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#define interrupt ((volatile INT_t ) INT0_VirtualAddress)
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#define gpio ((volatile GPIO_t) GPIO0_VirtualAddress)
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#define IDT_CLOCK_MULT 2
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#define MIPS_CPU_TIMER_IRQ 7
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/* Interrupt Controller */
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#define IC_GROUP0_PEND (RC32434_REG_BASE + 0x38000)
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#define IC_GROUP0_MASK (RC32434_REG_BASE + 0x38008)
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#define IC_GROUP_OFFSET 0x0C
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#define NUM_INTR_GROUPS 5
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/* 16550 UARTs */
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#define GROUP0_IRQ_BASE 8 /* GRP2 IRQ numbers start here */
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#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) /* GRP3 IRQ numbers start here */
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#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) /* GRP4 IRQ numbers start here */
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#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32) /* GRP5 IRQ numbers start here */
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#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32)
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#ifdef __MIPSEB__
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#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58003)
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#else
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#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58000)
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#endif
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#define RC32434_UART0_IRQ GROUP3_IRQ_BASE + 0
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// #define EB434_UART1_IRQ GROUP4_IRQ_BASE + 11
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#define local_readl(addr) __raw_readl(addr)
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#define local_writel(l,addr) __raw_writel(l,addr)
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/* cpu pipeline flush */
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static inline void rc32434_sync(void)
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{
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__asm__ volatile ("sync");
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}
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static inline void rc32434_sync_udelay(int us)
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{
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__asm__ volatile ("sync");
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udelay(us);
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}
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static inline void rc32434_sync_delay(int ms)
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{
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__asm__ volatile ("sync");
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mdelay(ms);
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}
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/*
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* C access to CLZ and CLO instructions
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* (count leading zeroes/ones).
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*/
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static inline int rc32434_clz(unsigned long val)
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{
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int ret;
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__asm__ volatile (
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".set\tnoreorder\n\t"
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".set\tnoat\n\t"
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".set\tmips32\n\t"
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"clz\t%0,%1\n\t"
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".set\tmips0\n\t"
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".set\tat\n\t"
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".set\treorder"
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: "=r" (ret)
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: "r" (val));
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return ret;
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}
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static inline int rc32434_clo(unsigned long val)
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{
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int ret;
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__asm__ volatile (
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".set\tnoreorder\n\t"
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".set\tnoat\n\t"
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".set\tmips32\n\t"
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"clo\t%0,%1\n\t"
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".set\tmips0\n\t"
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".set\tat\n\t"
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".set\treorder"
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: "=r" (ret)
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: "r" (val));
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return ret;
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}
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#endif /* _RC32434_H_ */
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