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Upstream commit be14811c03cf2 "pinctrl/lantiq: introduce new dedicated devicetree bindings" allows us to use each pin in the pinmux. This is useful for example in the "spi" group which contains some pins which are inputs, and some which are outputs. These can only be used once the new compatible strings for the pinctrl node are used. Additionally 0150-lantiq-pinctrl-xway.patch and the "GPIO PORT3 fix" (which was part of 0012-pinctrl-lantiq-fix-up-pinmux.patch) were replaced with their upstream variants which are also in 4.5. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> SVN-Revision: 48283
29 lines
989 B
Diff
29 lines
989 B
Diff
From 57b588c950b7e04e0f22393ad439299ba4fda9c3 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Thu, 26 Nov 2015 11:00:09 +0100
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Subject: [PATCH] pinctrl/lantiq: Fix GPIO Setup of GPIO Port3
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Some special handling of GPIO Port 3 is needed because of
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some hardware thingofabob.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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Signed-off-by: Martin Schiller <mschiller@tdt.de>
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Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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---
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drivers/pinctrl/pinctrl-xway.c | 4 ++++
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1 file changed, 4 insertions(+)
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--- a/drivers/pinctrl/pinctrl-xway.c
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+++ b/drivers/pinctrl/pinctrl-xway.c
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@@ -1570,6 +1570,10 @@ static int xway_gpio_dir_out(struct gpio
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{
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struct ltq_pinmux_info *info = dev_get_drvdata(chip->dev);
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+ if (PORT(pin) == PORT3)
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+ gpio_setbit(info->membase[0], GPIO3_OD, PORT_PIN(pin));
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+ else
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+ gpio_setbit(info->membase[0], GPIO_OD(pin), PORT_PIN(pin));
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gpio_setbit(info->membase[0], GPIO_DIR(pin), PORT_PIN(pin));
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xway_gpio_set(chip, pin, val);
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