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6be0da90a1
Removed upstreamed/solved elsewhere upstream: - 0001-MIPS-ralink-Add-rt3352-SPI_CS1-pinmux.patch - 0002-MIPS-pci-rt2880-set-pci-controller-of_node.patch - 0004-MIPS-ralink-add-MT7621-pcie-driver.patch - 0009-PCI-MIPS-enable-PCIe-on-MT7688.patch - 0025-pinctrl-ralink-add-pinctrl-driver.patch - 0028-GPIO-ralink-add-mt7621-gpio-controller.patch - 0043-spi-add-mt7621-support.patch - 0045-i2c-add-mt7621-driver.patch - 0047-DMA-ralink-add-rt2880-dma-engine.patch - 0053-mtd-spi-nor-add-w25q256-3b-mode-switch.patch - 0054-mtd-spi-nor-w25q256-respect-default-mode.patch - 0099-pci-mt7620.patch - 304-spi-nor-enable-4B-opcodes-for-mx25l25635f.patch Removed because of the new NAND driver: - 0038-Revert-mtd-nand-Remove-unused-chip-write_page-hook.patch - 0039-mtd-add-mt7621-nand-support.patch - 0040-nand-hack.patch Remove patch that no longer applies (needs rework): - 0034-NET-multi-phy-support.patch Signed-off-by: DENG Qingfang <dengqf6@mail2.sysu.edu.cn>
22 lines
704 B
Diff
22 lines
704 B
Diff
--- a/arch/mips/pci/pci-mt7620.c
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+++ b/arch/mips/pci/pci-mt7620.c
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@@ -32,6 +32,7 @@
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#define PPLL_CFG1 0x9c
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#define PPLL_DRV 0xa0
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+#define PPLL_LD BIT(23)
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#define PDRV_SW_SET BIT(31)
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#define LC_CKDRVPD BIT(19)
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#define LC_CKDRVOHZ BIT(18)
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@@ -239,8 +240,8 @@ static int mt7620_pci_hw_init(struct pla
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rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
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mdelay(100);
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- if (!(rt_sysc_r32(PPLL_CFG1) & PDRV_SW_SET)) {
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- dev_err(&pdev->dev, "MT7620 PPLL unlock\n");
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+ if (!(rt_sysc_r32(PPLL_CFG1) & PPLL_LD)) {
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+ dev_err(&pdev->dev, "MT7620 PPLL is unlocked, aborting init\n");
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reset_control_assert(rstpcie0);
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rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
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return -1;
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