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7903a9219c
A newer clk and cpufreq drivers for ipq806x platform had been sent upstream. A change that i have noticed is that now it's possible to set min, cur and max frequencies from sysfs (previously it was bugged and caused nothing). Following patches are removed: - 0036-clk-Avoid-sending-high-rates-to-downstream-clocks-du.patch - seems it was dropped from the patchset by current committer. - 0044-clk-qcom-krait-Remove-CLK_IS_ROOT.patch - already applied to the driver itself in the corresponding patch. - 0057-clk-qcom-Add-regmap-mux-div-clocks-support.patch - seem to be irrelevant to ipq806x. Signed-off-by: Pavel Kubelun <be.dissent@gmail.com>
26 lines
828 B
Diff
26 lines
828 B
Diff
From a16fcf911a020e46439a3bb3e702463fc3159831 Mon Sep 17 00:00:00 2001
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From: Abhishek Sahu <absahu@codeaurora.org>
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Date: Wed, 18 Nov 2015 12:38:56 +0530
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Subject: [PATCH 62/69] ipq806x: gcc: Added the enable regs and mask for PRNG
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kernel got hanged while reading from /dev/hwrng at the
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time of PRNG clock enable
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Change-Id: I89856c7e19e6639508e6a2774304583a3ec91172
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Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
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---
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drivers/clk/qcom/gcc-ipq806x.c | 2 ++
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1 file changed, 2 insertions(+)
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--- a/drivers/clk/qcom/gcc-ipq806x.c
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+++ b/drivers/clk/qcom/gcc-ipq806x.c
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@@ -1233,6 +1233,8 @@ static struct clk_rcg prng_src = {
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.parent_map = gcc_pxo_pll8_map,
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},
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.clkr = {
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+ .enable_reg = 0x2e80,
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+ .enable_mask = BIT(11),
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.hw.init = &(struct clk_init_data){
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.name = "prng_src",
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.parent_names = gcc_pxo_pll8,
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