1
0
mirror of https://git.openwrt.org/openwrt/openwrt.git synced 2024-10-20 06:28:12 +02:00
openwrt/target/linux/mvebu/patches-4.19/540-phy-fix-build-breakage-add-PHY_MODE_SATA.patch
Scott Roberts d2a1075973 mvebu: backport mvneta and comphy from linux 5.x
These patches backport support for the ARMADA 3700 COMPHY driver.
Also backported is the mvneta driver.  This will allow switching
the SGMII speed using SMC calls.  To support this you must update
the firmware using Marvells 18.12 version (this has now been
upstreamed).  The mvneta driver allows 2500basex and 2500baset.

Signed-off-by: Scott Roberts <ttocsr@gmail.com>
2019-10-12 23:43:08 +02:00

46 lines
1.5 KiB
Diff

From e1706720408e72fb883f6b151c2b3b23d8e7e5b2 Mon Sep 17 00:00:00 2001
From: John Hubbard <jhubbard@nvidia.com>
Date: Sat, 12 Jan 2019 17:29:09 -0800
Subject: [PATCH] phy: fix build breakage: add PHY_MODE_SATA
Commit 49e54187ae0b ("ata: libahci_platform: comply to PHY framework") uses
the PHY_MODE_SATA, but that enum had not yet been added. This caused a
build failure for me, with today's linux.git.
Also, there is a potentially conflicting (mis-named) PHY_MODE_SATA, hiding
in the Marvell Berlin SATA PHY driver.
Fix the build by:
1) Renaming Marvell's defined value to a more scoped name,
in order to avoid any potential conflicts: PHY_BERLIN_MODE_SATA.
2) Adding the missing enum, which was going to be added anyway as part
of [1].
[1] https://lkml.kernel.org/r/20190108163124.6409-3-miquel.raynal@bootlin.com
Fixes: 49e54187ae0b ("ata: libahci_platform: comply to PHY framework")
Signed-off-by: John Hubbard <jhubbard@nvidia.com>
Acked-by: Jens Axboe <axboe@kernel.dk>
Acked-by: Olof Johansson <olof@lixom.net>
Cc: Grzegorz Jaszczyk <jaz@semihalf.com>
Cc: Miquel Raynal <miquel.raynal@bootlin.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
---
include/linux/phy/phy.h | 1 +
1 file changed, 1 insertion(+)
--- a/include/linux/phy/phy.h
+++ b/include/linux/phy/phy.h
@@ -43,6 +43,7 @@ enum phy_mode {
PHY_MODE_UFS_HS_B,
PHY_MODE_PCIE,
PHY_MODE_ETHERNET,
+ PHY_MODE_SATA
};
/**