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24de7c29e5
Backport below changes for I2C QUP driver from v4.17: 0668bc44a426 i2c: qup: fix copyrights and update to SPDX identifier 7239872fb340 i2c: qup: fixed releasing dma without flush operation completion eb422b539c1f i2c: qup: minor code reorganization for use_dma 6d5f37f166bb i2c: qup: remove redundant variables for BAM SG count c5adc0fa63a9 i2c: qup: schedule EOT and FLUSH tags at the end of transfer 7e6c35fe602d i2c: qup: fix the transfer length for BAM RX EOT FLUSH tags 3f450d3eea14 i2c: qup: proper error handling for i2c error in BAM mode 08f15963bc75 i2c: qup: use the complete transfer length to choose DMA mode ecb6e1e5f435 i2c: qup: change completion timeout according to transfer length 6f2f0f6465ac i2c: qup: fix buffer overflow for multiple msg of maximum xfer len f7714b4e451b i2c: qup: send NACK for last read sub transfers fbfab1ab0658 i2c: qup: reorganization of driver code to remove polling for qup v1 7545c7dba169 i2c: qup: reorganization of driver code to remove polling for qup v2 This fixes various I2C issues observed on AP120C-AC board equipped with Atmel/Microchip AT97SC3205T TPM module. Tested-by: Christian Lamparter <chunkeey@gmail.com> Signed-off-by: Piotr Dymacz <pepe2k@gmail.com>
62 lines
2.0 KiB
Diff
62 lines
2.0 KiB
Diff
From ecb6e1e5f4352055a5761b945a833a925d51bf8d Mon Sep 17 00:00:00 2001
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From: Abhishek Sahu <absahu@codeaurora.org>
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Date: Mon, 12 Mar 2018 18:44:58 +0530
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Subject: [PATCH 09/13] i2c: qup: change completion timeout according to
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transfer length
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Currently the completion timeout is being taken according to
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maximum transfer length which is too high if SCL is operating in
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high frequency. This patch calculates timeout on the basis of
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one-byte transfer time and uses the same for completion timeout.
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Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
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Reviewed-by: Andy Gross <andy.gross@linaro.org>
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Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
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---
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drivers/i2c/busses/i2c-qup.c | 13 ++++++++++---
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1 file changed, 10 insertions(+), 3 deletions(-)
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--- a/drivers/i2c/busses/i2c-qup.c
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+++ b/drivers/i2c/busses/i2c-qup.c
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@@ -121,8 +121,12 @@
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#define MX_TX_RX_LEN SZ_64K
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#define MX_BLOCKS (MX_TX_RX_LEN / QUP_READ_LIMIT)
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-/* Max timeout in ms for 32k bytes */
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-#define TOUT_MAX 300
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+/*
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+ * Minimum transfer timeout for i2c transfers in seconds. It will be added on
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+ * the top of maximum transfer time calculated from i2c bus speed to compensate
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+ * the overheads.
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+ */
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+#define TOUT_MIN 2
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/* Default values. Use these if FW query fails */
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#define DEFAULT_CLK_FREQ 100000
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@@ -163,6 +167,7 @@ struct qup_i2c_dev {
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int in_blk_sz;
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unsigned long one_byte_t;
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+ unsigned long xfer_timeout;
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struct qup_i2c_block blk;
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struct i2c_msg *msg;
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@@ -849,7 +854,7 @@ static int qup_i2c_bam_do_xfer(struct qu
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dma_async_issue_pending(qup->brx.dma);
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}
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- if (!wait_for_completion_timeout(&qup->xfer, TOUT_MAX * HZ)) {
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+ if (!wait_for_completion_timeout(&qup->xfer, qup->xfer_timeout)) {
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dev_err(qup->dev, "normal trans timed out\n");
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ret = -ETIMEDOUT;
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}
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@@ -1605,6 +1610,8 @@ nodma:
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*/
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one_bit_t = (USEC_PER_SEC / clk_freq) + 1;
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qup->one_byte_t = one_bit_t * 9;
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+ qup->xfer_timeout = TOUT_MIN * HZ +
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+ usecs_to_jiffies(MX_TX_RX_LEN * qup->one_byte_t);
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dev_dbg(qup->dev, "IN:block:%d, fifo:%d, OUT:block:%d, fifo:%d\n",
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qup->in_blk_sz, qup->in_fifo_sz,
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