mirror of
https://git.openwrt.org/openwrt/openwrt.git
synced 2024-10-19 14:08:17 +02:00
b2c9c4dda2
This patch copies over refreshed config and patches from 5.10 with the following changes: - dropped superfluous tc654/tc655 variant detection patch (tc654 support will become available upstream starting with 5.17-rc7+). - dropped xhci msi(x) workaround... as the broken MSI(X) is now gone. - dropped dwc2 workaround since the driver was fixed and it works without it. Please note: Netgear WNDAP660 & WNDAP620 users: Due to the kernel's size increase, uboot will likely break because it is overwrite the kernel during decompression. To fix this (and debrick affected devices, no reflash necessary), attach the RJ45-Serial-Console cable and enter the following in the uboot prompt during bootup: setenv kernel_addr_r 1100000 saveenv run bootcmd to restore the old/previous behavior: setenv kernel_addr_r 600000 saveenv run bootcmd Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
52 lines
1.8 KiB
Diff
52 lines
1.8 KiB
Diff
--- a/arch/powerpc/platforms/4xx/pci.c
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+++ b/arch/powerpc/platforms/4xx/pci.c
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@@ -1060,15 +1060,24 @@ static int __init apm821xx_pciex_init_po
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u32 val;
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/*
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- * Do a software reset on PCIe ports.
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- * This code is to fix the issue that pci drivers doesn't re-assign
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- * bus number for PCIE devices after Uboot
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- * scanned and configured all the buses (eg. PCIE NIC IntelPro/1000
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- * PT quad port, SAS LSI 1064E)
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+ * Only reset the PHY when no link is currently established.
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+ * This is for the Atheros PCIe board which has problems to establish
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+ * the link (again) after this PHY reset. All other currently tested
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+ * PCIe boards don't show this problem.
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*/
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-
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- mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x0);
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- mdelay(10);
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+ val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP);
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+ if (!(val & 0x00001000)) {
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+ /*
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+ * Do a software reset on PCIe ports.
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+ * This code is to fix the issue that pci drivers doesn't re-assign
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+ * bus number for PCIE devices after Uboot
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+ * scanned and configured all the buses (eg. PCIE NIC IntelPro/1000
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+ * PT quad port, SAS LSI 1064E)
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+ */
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+
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+ mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x0);
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+ mdelay(10);
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+ }
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if (port->endpoint)
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val = PTYPE_LEGACY_ENDPOINT << 20;
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@@ -1085,9 +1094,12 @@ static int __init apm821xx_pciex_init_po
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mtdcri(SDR0, PESDR0_460EX_L0DRV, 0x00000130);
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mtdcri(SDR0, PESDR0_460EX_L0CLK, 0x00000006);
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- mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x10000000);
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- mdelay(50);
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- mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x30000000);
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+ val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP);
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+ if (!(val & 0x00001000)) {
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+ mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x10000000);
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+ mdelay(50);
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+ mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x30000000);
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+ }
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mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
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mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) |
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