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https://git.openwrt.org/openwrt/openwrt.git
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2ad898e091
Removed upstreamed: generic/backport-6.1/789-STABLE-01-net-dsa-mt7530-prevent-possible-incorrect-XTAL-frequ.patch [1] generic/backport-6.1/789-STABLE-02-net-dsa-mt7530-fix-link-local-frames-that-ingress-vl.patch [2] generic/backport-6.1/789-STABLE-03-net-dsa-mt7530-fix-handling-of-all-link-local-frames.patch [3] generic/pending-6.1/735-net-mediatek-mtk_eth_soc-release-MAC_MCR_FORCE_LINK-.patch [4] generic/pending-6.1/736-net-ethernet-mtk_eth_soc-fix-PPE-hanging-issue.patch [5] Manual adjusted the following patches: mediatek/patches-6.1/100-dts-update-mt7622-rfb1.patch 1. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.1.83&id=be4512b9ac6fc53e1ca8daccbda84f643215c547 2. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.1.83&id=f1fa919ea59655f73cb3972264e157b8831ba546 3. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.1.83&id=86c0c154a759f2af9612a04bdf29110f02dce956 4. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.1.83&id=6b62bad2da1b338f452a9380639fc9b093d75a25 5. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.1.83&id=f78807362828ad01db2a9ed005bf79501b620f27 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
551 lines
20 KiB
Diff
551 lines
20 KiB
Diff
From 5d8d05fbf804b4485646d39551ac27452e45afd3 Mon Sep 17 00:00:00 2001
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From: Lorenzo Bianconi <lorenzo@kernel.org>
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Date: Tue, 25 Jul 2023 01:52:02 +0100
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Subject: [PATCH 099/250] net: ethernet: mtk_eth_soc: add version in
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mtk_soc_data
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Introduce version field in mtk_soc_data data structure in order to
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make mtk_eth driver easier to maintain for chipset configuration
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codebase. Get rid of MTK_NETSYS_V2 bit in chip capabilities.
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This is a preliminary patch to introduce support for MT7988 SoC.
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Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
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Signed-off-by: Daniel Golle <daniel@makrotopia.org>
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Link: https://lore.kernel.org/r/e52fae302ca135436e5cdd26d38d87be2da63055.1690246066.git.daniel@makrotopia.org
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Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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---
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drivers/net/ethernet/mediatek/mtk_eth_soc.c | 55 +++++++++++--------
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drivers/net/ethernet/mediatek/mtk_eth_soc.h | 36 +++++++-----
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drivers/net/ethernet/mediatek/mtk_ppe.c | 18 +++---
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.../net/ethernet/mediatek/mtk_ppe_offload.c | 2 +-
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drivers/net/ethernet/mediatek/mtk_wed.c | 4 +-
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5 files changed, 66 insertions(+), 49 deletions(-)
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--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
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+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
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@@ -579,7 +579,7 @@ static void mtk_set_queue_speed(struct m
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FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) |
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FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) |
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MTK_QTX_SCH_LEAKY_BUCKET_SIZE;
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- if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
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+ if (mtk_is_netsys_v1(eth))
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val |= MTK_QTX_SCH_LEAKY_BUCKET_EN;
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if (IS_ENABLED(CONFIG_SOC_MT7621)) {
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@@ -954,7 +954,7 @@ static bool mtk_rx_get_desc(struct mtk_e
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rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
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rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
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rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
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- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
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+ if (mtk_is_netsys_v2_or_greater(eth)) {
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rxd->rxd5 = READ_ONCE(dma_rxd->rxd5);
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rxd->rxd6 = READ_ONCE(dma_rxd->rxd6);
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}
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@@ -1012,7 +1012,7 @@ static int mtk_init_fq_dma(struct mtk_et
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txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE);
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txd->txd4 = 0;
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- if (MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V2)) {
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+ if (mtk_is_netsys_v2_or_greater(eth)) {
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txd->txd5 = 0;
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txd->txd6 = 0;
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txd->txd7 = 0;
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@@ -1203,7 +1203,7 @@ static void mtk_tx_set_dma_desc(struct n
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struct mtk_mac *mac = netdev_priv(dev);
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struct mtk_eth *eth = mac->hw;
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- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
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+ if (mtk_is_netsys_v2_or_greater(eth))
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mtk_tx_set_dma_desc_v2(dev, txd, info);
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else
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mtk_tx_set_dma_desc_v1(dev, txd, info);
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@@ -1510,7 +1510,7 @@ static void mtk_update_rx_cpu_idx(struct
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static bool mtk_page_pool_enabled(struct mtk_eth *eth)
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{
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- return MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2);
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+ return eth->soc->version == 2;
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}
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static struct page_pool *mtk_create_page_pool(struct mtk_eth *eth,
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@@ -1852,7 +1852,7 @@ static int mtk_poll_rx(struct napi_struc
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break;
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/* find out which mac the packet come from. values start at 1 */
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- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
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+ if (mtk_is_netsys_v2_or_greater(eth))
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mac = RX_DMA_GET_SPORT_V2(trxd.rxd5) - 1;
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else if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) &&
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!(trxd.rxd4 & RX_DMA_SPECIAL_TAG))
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@@ -1948,7 +1948,7 @@ static int mtk_poll_rx(struct napi_struc
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skb->dev = netdev;
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bytes += skb->len;
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- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
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+ if (mtk_is_netsys_v2_or_greater(eth)) {
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reason = FIELD_GET(MTK_RXD5_PPE_CPU_REASON, trxd.rxd5);
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hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY;
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if (hash != MTK_RXD5_FOE_ENTRY)
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@@ -1973,8 +1973,8 @@ static int mtk_poll_rx(struct napi_struc
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/* When using VLAN untagging in combination with DSA, the
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* hardware treats the MTK special tag as a VLAN and untags it.
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*/
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- if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) &&
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- (trxd.rxd2 & RX_DMA_VTAG) && netdev_uses_dsa(netdev)) {
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+ if (mtk_is_netsys_v1(eth) && (trxd.rxd2 & RX_DMA_VTAG) &&
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+ netdev_uses_dsa(netdev)) {
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unsigned int port = RX_DMA_VPID(trxd.rxd3) & GENMASK(2, 0);
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if (port < ARRAY_SIZE(eth->dsa_meta) &&
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@@ -2284,7 +2284,7 @@ static int mtk_tx_alloc(struct mtk_eth *
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txd->txd2 = next_ptr;
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txd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
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txd->txd4 = 0;
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- if (MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V2)) {
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+ if (mtk_is_netsys_v2_or_greater(eth)) {
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txd->txd5 = 0;
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txd->txd6 = 0;
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txd->txd7 = 0;
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@@ -2337,14 +2337,14 @@ static int mtk_tx_alloc(struct mtk_eth *
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FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) |
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FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) |
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MTK_QTX_SCH_LEAKY_BUCKET_SIZE;
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- if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
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+ if (mtk_is_netsys_v1(eth))
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val |= MTK_QTX_SCH_LEAKY_BUCKET_EN;
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mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs);
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ofs += MTK_QTX_OFFSET;
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}
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val = MTK_QDMA_TX_SCH_MAX_WFQ | (MTK_QDMA_TX_SCH_MAX_WFQ << 16);
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mtk_w32(eth, val, soc->reg_map->qdma.tx_sch_rate);
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- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
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+ if (mtk_is_netsys_v2_or_greater(eth))
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mtk_w32(eth, val, soc->reg_map->qdma.tx_sch_rate + 4);
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} else {
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mtk_w32(eth, ring->phys_pdma, MT7628_TX_BASE_PTR0);
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@@ -2473,7 +2473,7 @@ static int mtk_rx_alloc(struct mtk_eth *
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rxd->rxd3 = 0;
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rxd->rxd4 = 0;
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- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
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+ if (mtk_is_netsys_v2_or_greater(eth)) {
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rxd->rxd5 = 0;
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rxd->rxd6 = 0;
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rxd->rxd7 = 0;
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@@ -3024,7 +3024,7 @@ static int mtk_start_dma(struct mtk_eth
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MTK_TX_BT_32DWORDS | MTK_NDP_CO_PRO |
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MTK_RX_2B_OFFSET | MTK_TX_WB_DDONE;
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- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
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+ if (mtk_is_netsys_v2_or_greater(eth))
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val |= MTK_MUTLI_CNT | MTK_RESV_BUF |
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MTK_WCOMP_EN | MTK_DMAD_WR_WDONE |
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MTK_CHK_DDONE_EN | MTK_LEAKY_BUCKET_EN;
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@@ -3166,7 +3166,7 @@ static int mtk_open(struct net_device *d
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phylink_start(mac->phylink);
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netif_tx_start_all_queues(dev);
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- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
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+ if (mtk_is_netsys_v2_or_greater(eth))
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return 0;
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if (mtk_uses_dsa(dev) && !eth->prog) {
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@@ -3431,7 +3431,7 @@ static void mtk_hw_reset(struct mtk_eth
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{
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u32 val;
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- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
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+ if (mtk_is_netsys_v2_or_greater(eth)) {
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regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0);
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val = RSTCTRL_PPE0_V2;
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} else {
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@@ -3443,7 +3443,7 @@ static void mtk_hw_reset(struct mtk_eth
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ethsys_reset(eth, RSTCTRL_ETH | RSTCTRL_FE | val);
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- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
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+ if (mtk_is_netsys_v2_or_greater(eth))
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regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN,
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0x3ffffff);
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}
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@@ -3469,7 +3469,7 @@ static void mtk_hw_warm_reset(struct mtk
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return;
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}
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- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
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+ if (mtk_is_netsys_v2_or_greater(eth))
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rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0_V2;
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else
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rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0;
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@@ -3639,7 +3639,7 @@ static int mtk_hw_init(struct mtk_eth *e
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else
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mtk_hw_reset(eth);
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- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
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+ if (mtk_is_netsys_v2_or_greater(eth)) {
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/* Set FE to PDMAv2 if necessary */
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val = mtk_r32(eth, MTK_FE_GLO_MISC);
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mtk_w32(eth, val | BIT(4), MTK_FE_GLO_MISC);
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@@ -3676,7 +3676,7 @@ static int mtk_hw_init(struct mtk_eth *e
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*/
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val = mtk_r32(eth, MTK_CDMQ_IG_CTRL);
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mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL);
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- if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
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+ if (mtk_is_netsys_v1(eth)) {
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val = mtk_r32(eth, MTK_CDMP_IG_CTRL);
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mtk_w32(eth, val | MTK_CDMP_STAG_EN, MTK_CDMP_IG_CTRL);
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@@ -3698,7 +3698,7 @@ static int mtk_hw_init(struct mtk_eth *e
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mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->qdma.int_grp + 4);
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mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
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- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
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+ if (mtk_is_netsys_v2_or_greater(eth)) {
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/* PSE should not drop port8 and port9 packets from WDMA Tx */
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mtk_w32(eth, 0x00000300, PSE_DROP_CFG);
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@@ -4487,7 +4487,7 @@ static int mtk_probe(struct platform_dev
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}
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}
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- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
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+ if (mtk_is_netsys_v2_or_greater(eth)) {
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res) {
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err = -EINVAL;
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@@ -4595,9 +4595,8 @@ static int mtk_probe(struct platform_dev
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}
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if (eth->soc->offload_version) {
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- u32 num_ppe;
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+ u32 num_ppe = mtk_is_netsys_v2_or_greater(eth) ? 2 : 1;
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- num_ppe = MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) ? 2 : 1;
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num_ppe = min_t(u32, ARRAY_SIZE(eth->ppe), num_ppe);
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for (i = 0; i < num_ppe; i++) {
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u32 ppe_addr = eth->soc->reg_map->ppe_base + i * 0x400;
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@@ -4689,6 +4688,7 @@ static const struct mtk_soc_data mt2701_
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.hw_features = MTK_HW_FEATURES,
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.required_clks = MT7623_CLKS_BITMAP,
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.required_pctl = true,
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+ .version = 1,
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.txrx = {
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.txd_size = sizeof(struct mtk_tx_dma),
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.rxd_size = sizeof(struct mtk_rx_dma),
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@@ -4705,6 +4705,7 @@ static const struct mtk_soc_data mt7621_
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.hw_features = MTK_HW_FEATURES,
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.required_clks = MT7621_CLKS_BITMAP,
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.required_pctl = false,
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+ .version = 1,
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.offload_version = 1,
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.hash_offset = 2,
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.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
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@@ -4725,6 +4726,7 @@ static const struct mtk_soc_data mt7622_
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.hw_features = MTK_HW_FEATURES,
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.required_clks = MT7622_CLKS_BITMAP,
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.required_pctl = false,
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+ .version = 1,
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.offload_version = 2,
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.hash_offset = 2,
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.has_accounting = true,
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@@ -4745,6 +4747,7 @@ static const struct mtk_soc_data mt7623_
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.hw_features = MTK_HW_FEATURES,
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.required_clks = MT7623_CLKS_BITMAP,
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.required_pctl = true,
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+ .version = 1,
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.offload_version = 1,
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.hash_offset = 2,
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.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
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@@ -4767,6 +4770,7 @@ static const struct mtk_soc_data mt7629_
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.required_clks = MT7629_CLKS_BITMAP,
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.required_pctl = false,
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.has_accounting = true,
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+ .version = 1,
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.txrx = {
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.txd_size = sizeof(struct mtk_tx_dma),
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.rxd_size = sizeof(struct mtk_rx_dma),
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@@ -4784,6 +4788,7 @@ static const struct mtk_soc_data mt7981_
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.hw_features = MTK_HW_FEATURES,
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.required_clks = MT7981_CLKS_BITMAP,
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.required_pctl = false,
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+ .version = 2,
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.offload_version = 2,
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.hash_offset = 4,
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.has_accounting = true,
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@@ -4805,6 +4810,7 @@ static const struct mtk_soc_data mt7986_
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.hw_features = MTK_HW_FEATURES,
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.required_clks = MT7986_CLKS_BITMAP,
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.required_pctl = false,
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+ .version = 2,
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.offload_version = 2,
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.hash_offset = 4,
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.has_accounting = true,
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@@ -4825,6 +4831,7 @@ static const struct mtk_soc_data rt5350_
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.hw_features = MTK_HW_FEATURES_MT7628,
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.required_clks = MT7628_CLKS_BITMAP,
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.required_pctl = false,
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+ .version = 1,
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.txrx = {
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.txd_size = sizeof(struct mtk_tx_dma),
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.rxd_size = sizeof(struct mtk_rx_dma),
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--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
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+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
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@@ -820,7 +820,6 @@ enum mkt_eth_capabilities {
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MTK_SHARED_INT_BIT,
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MTK_TRGMII_MT7621_CLK_BIT,
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MTK_QDMA_BIT,
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- MTK_NETSYS_V2_BIT,
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MTK_SOC_MT7628_BIT,
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MTK_RSTCTRL_PPE1_BIT,
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MTK_U3_COPHY_V2_BIT,
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@@ -855,7 +854,6 @@ enum mkt_eth_capabilities {
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#define MTK_SHARED_INT BIT(MTK_SHARED_INT_BIT)
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#define MTK_TRGMII_MT7621_CLK BIT(MTK_TRGMII_MT7621_CLK_BIT)
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#define MTK_QDMA BIT(MTK_QDMA_BIT)
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-#define MTK_NETSYS_V2 BIT(MTK_NETSYS_V2_BIT)
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#define MTK_SOC_MT7628 BIT(MTK_SOC_MT7628_BIT)
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#define MTK_RSTCTRL_PPE1 BIT(MTK_RSTCTRL_PPE1_BIT)
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#define MTK_U3_COPHY_V2 BIT(MTK_U3_COPHY_V2_BIT)
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@@ -934,11 +932,11 @@ enum mkt_eth_capabilities {
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#define MT7981_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \
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MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
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MTK_MUX_U3_GMAC2_TO_QPHY | MTK_U3_COPHY_V2 | \
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- MTK_NETSYS_V2 | MTK_RSTCTRL_PPE1)
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+ MTK_RSTCTRL_PPE1)
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#define MT7986_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \
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MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
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- MTK_NETSYS_V2 | MTK_RSTCTRL_PPE1)
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+ MTK_RSTCTRL_PPE1)
|
|
|
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struct mtk_tx_dma_desc_info {
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dma_addr_t addr;
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|
@@ -1009,6 +1007,7 @@ struct mtk_reg_map {
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* @required_pctl A bool value to show whether the SoC requires
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* the extra setup for those pins used by GMAC.
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* @hash_offset Flow table hash offset.
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|
+ * @version SoC version.
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* @foe_entry_size Foe table entry size.
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* @has_accounting Bool indicating support for accounting of
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* offloaded flows.
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@@ -1027,6 +1026,7 @@ struct mtk_soc_data {
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bool required_pctl;
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u8 offload_version;
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u8 hash_offset;
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+ u8 version;
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u16 foe_entry_size;
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|
netdev_features_t hw_features;
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bool has_accounting;
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|
@@ -1183,6 +1183,16 @@ struct mtk_mac {
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/* the struct describing the SoC. these are declared in the soc_xyz.c files */
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extern const struct of_device_id of_mtk_match[];
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|
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|
+static inline bool mtk_is_netsys_v1(struct mtk_eth *eth)
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+{
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|
+ return eth->soc->version == 1;
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+}
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+
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+static inline bool mtk_is_netsys_v2_or_greater(struct mtk_eth *eth)
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+{
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+ return eth->soc->version > 1;
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+}
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+
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|
static inline struct mtk_foe_entry *
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mtk_foe_get_entry(struct mtk_ppe *ppe, u16 hash)
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|
{
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|
@@ -1193,7 +1203,7 @@ mtk_foe_get_entry(struct mtk_ppe *ppe, u
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|
|
|
static inline u32 mtk_get_ib1_ts_mask(struct mtk_eth *eth)
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|
{
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- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
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+ if (mtk_is_netsys_v2_or_greater(eth))
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return MTK_FOE_IB1_BIND_TIMESTAMP_V2;
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|
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|
return MTK_FOE_IB1_BIND_TIMESTAMP;
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|
@@ -1201,7 +1211,7 @@ static inline u32 mtk_get_ib1_ts_mask(st
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|
|
|
static inline u32 mtk_get_ib1_ppoe_mask(struct mtk_eth *eth)
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|
{
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|
- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
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|
+ if (mtk_is_netsys_v2_or_greater(eth))
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|
return MTK_FOE_IB1_BIND_PPPOE_V2;
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|
|
|
return MTK_FOE_IB1_BIND_PPPOE;
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|
@@ -1209,7 +1219,7 @@ static inline u32 mtk_get_ib1_ppoe_mask(
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|
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|
static inline u32 mtk_get_ib1_vlan_tag_mask(struct mtk_eth *eth)
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{
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|
- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
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|
+ if (mtk_is_netsys_v2_or_greater(eth))
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return MTK_FOE_IB1_BIND_VLAN_TAG_V2;
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|
|
|
return MTK_FOE_IB1_BIND_VLAN_TAG;
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|
@@ -1217,7 +1227,7 @@ static inline u32 mtk_get_ib1_vlan_tag_m
|
|
|
|
static inline u32 mtk_get_ib1_vlan_layer_mask(struct mtk_eth *eth)
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|
{
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|
- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
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|
+ if (mtk_is_netsys_v2_or_greater(eth))
|
|
return MTK_FOE_IB1_BIND_VLAN_LAYER_V2;
|
|
|
|
return MTK_FOE_IB1_BIND_VLAN_LAYER;
|
|
@@ -1225,7 +1235,7 @@ static inline u32 mtk_get_ib1_vlan_layer
|
|
|
|
static inline u32 mtk_prep_ib1_vlan_layer(struct mtk_eth *eth, u32 val)
|
|
{
|
|
- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
|
|
+ if (mtk_is_netsys_v2_or_greater(eth))
|
|
return FIELD_PREP(MTK_FOE_IB1_BIND_VLAN_LAYER_V2, val);
|
|
|
|
return FIELD_PREP(MTK_FOE_IB1_BIND_VLAN_LAYER, val);
|
|
@@ -1233,7 +1243,7 @@ static inline u32 mtk_prep_ib1_vlan_laye
|
|
|
|
static inline u32 mtk_get_ib1_vlan_layer(struct mtk_eth *eth, u32 val)
|
|
{
|
|
- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
|
|
+ if (mtk_is_netsys_v2_or_greater(eth))
|
|
return FIELD_GET(MTK_FOE_IB1_BIND_VLAN_LAYER_V2, val);
|
|
|
|
return FIELD_GET(MTK_FOE_IB1_BIND_VLAN_LAYER, val);
|
|
@@ -1241,7 +1251,7 @@ static inline u32 mtk_get_ib1_vlan_layer
|
|
|
|
static inline u32 mtk_get_ib1_pkt_type_mask(struct mtk_eth *eth)
|
|
{
|
|
- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
|
|
+ if (mtk_is_netsys_v2_or_greater(eth))
|
|
return MTK_FOE_IB1_PACKET_TYPE_V2;
|
|
|
|
return MTK_FOE_IB1_PACKET_TYPE;
|
|
@@ -1249,7 +1259,7 @@ static inline u32 mtk_get_ib1_pkt_type_m
|
|
|
|
static inline u32 mtk_get_ib1_pkt_type(struct mtk_eth *eth, u32 val)
|
|
{
|
|
- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
|
|
+ if (mtk_is_netsys_v2_or_greater(eth))
|
|
return FIELD_GET(MTK_FOE_IB1_PACKET_TYPE_V2, val);
|
|
|
|
return FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, val);
|
|
@@ -1257,7 +1267,7 @@ static inline u32 mtk_get_ib1_pkt_type(s
|
|
|
|
static inline u32 mtk_get_ib2_multicast_mask(struct mtk_eth *eth)
|
|
{
|
|
- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
|
|
+ if (mtk_is_netsys_v2_or_greater(eth))
|
|
return MTK_FOE_IB2_MULTICAST_V2;
|
|
|
|
return MTK_FOE_IB2_MULTICAST;
|
|
--- a/drivers/net/ethernet/mediatek/mtk_ppe.c
|
|
+++ b/drivers/net/ethernet/mediatek/mtk_ppe.c
|
|
@@ -207,7 +207,7 @@ int mtk_foe_entry_prepare(struct mtk_eth
|
|
|
|
memset(entry, 0, sizeof(*entry));
|
|
|
|
- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
|
|
+ if (mtk_is_netsys_v2_or_greater(eth)) {
|
|
val = FIELD_PREP(MTK_FOE_IB1_STATE, MTK_FOE_STATE_BIND) |
|
|
FIELD_PREP(MTK_FOE_IB1_PACKET_TYPE_V2, type) |
|
|
FIELD_PREP(MTK_FOE_IB1_UDP, l4proto == IPPROTO_UDP) |
|
|
@@ -271,7 +271,7 @@ int mtk_foe_entry_set_pse_port(struct mt
|
|
u32 *ib2 = mtk_foe_entry_ib2(eth, entry);
|
|
u32 val = *ib2;
|
|
|
|
- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
|
|
+ if (mtk_is_netsys_v2_or_greater(eth)) {
|
|
val &= ~MTK_FOE_IB2_DEST_PORT_V2;
|
|
val |= FIELD_PREP(MTK_FOE_IB2_DEST_PORT_V2, port);
|
|
} else {
|
|
@@ -422,7 +422,7 @@ int mtk_foe_entry_set_wdma(struct mtk_et
|
|
struct mtk_foe_mac_info *l2 = mtk_foe_entry_l2(eth, entry);
|
|
u32 *ib2 = mtk_foe_entry_ib2(eth, entry);
|
|
|
|
- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
|
|
+ if (mtk_is_netsys_v2_or_greater(eth)) {
|
|
*ib2 &= ~MTK_FOE_IB2_PORT_MG_V2;
|
|
*ib2 |= FIELD_PREP(MTK_FOE_IB2_RX_IDX, txq) |
|
|
MTK_FOE_IB2_WDMA_WINFO_V2;
|
|
@@ -446,7 +446,7 @@ int mtk_foe_entry_set_queue(struct mtk_e
|
|
{
|
|
u32 *ib2 = mtk_foe_entry_ib2(eth, entry);
|
|
|
|
- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
|
|
+ if (mtk_is_netsys_v2_or_greater(eth)) {
|
|
*ib2 &= ~MTK_FOE_IB2_QID_V2;
|
|
*ib2 |= FIELD_PREP(MTK_FOE_IB2_QID_V2, queue);
|
|
*ib2 |= MTK_FOE_IB2_PSE_QOS_V2;
|
|
@@ -601,7 +601,7 @@ __mtk_foe_entry_commit(struct mtk_ppe *p
|
|
struct mtk_foe_entry *hwe;
|
|
u32 val;
|
|
|
|
- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
|
|
+ if (mtk_is_netsys_v2_or_greater(eth)) {
|
|
entry->ib1 &= ~MTK_FOE_IB1_BIND_TIMESTAMP_V2;
|
|
entry->ib1 |= FIELD_PREP(MTK_FOE_IB1_BIND_TIMESTAMP_V2,
|
|
timestamp);
|
|
@@ -617,7 +617,7 @@ __mtk_foe_entry_commit(struct mtk_ppe *p
|
|
hwe->ib1 = entry->ib1;
|
|
|
|
if (ppe->accounting) {
|
|
- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
|
|
+ if (mtk_is_netsys_v2_or_greater(eth))
|
|
val = MTK_FOE_IB2_MIB_CNT_V2;
|
|
else
|
|
val = MTK_FOE_IB2_MIB_CNT;
|
|
@@ -965,7 +965,7 @@ void mtk_ppe_start(struct mtk_ppe *ppe)
|
|
MTK_PPE_SCAN_MODE_CHECK_AGE) |
|
|
FIELD_PREP(MTK_PPE_TB_CFG_ENTRY_NUM,
|
|
MTK_PPE_ENTRIES_SHIFT);
|
|
- if (MTK_HAS_CAPS(ppe->eth->soc->caps, MTK_NETSYS_V2))
|
|
+ if (mtk_is_netsys_v2_or_greater(ppe->eth))
|
|
val |= MTK_PPE_TB_CFG_INFO_SEL;
|
|
ppe_w32(ppe, MTK_PPE_TB_CFG, val);
|
|
|
|
@@ -981,7 +981,7 @@ void mtk_ppe_start(struct mtk_ppe *ppe)
|
|
MTK_PPE_FLOW_CFG_IP4_NAPT |
|
|
MTK_PPE_FLOW_CFG_IP4_DSLITE |
|
|
MTK_PPE_FLOW_CFG_IP4_NAT_FRAG;
|
|
- if (MTK_HAS_CAPS(ppe->eth->soc->caps, MTK_NETSYS_V2))
|
|
+ if (mtk_is_netsys_v2_or_greater(ppe->eth))
|
|
val |= MTK_PPE_MD_TOAP_BYP_CRSN0 |
|
|
MTK_PPE_MD_TOAP_BYP_CRSN1 |
|
|
MTK_PPE_MD_TOAP_BYP_CRSN2 |
|
|
@@ -1023,7 +1023,7 @@ void mtk_ppe_start(struct mtk_ppe *ppe)
|
|
|
|
ppe_w32(ppe, MTK_PPE_DEFAULT_CPU_PORT, 0);
|
|
|
|
- if (MTK_HAS_CAPS(ppe->eth->soc->caps, MTK_NETSYS_V2)) {
|
|
+ if (mtk_is_netsys_v2_or_greater(ppe->eth)) {
|
|
ppe_w32(ppe, MTK_PPE_DEFAULT_CPU_PORT1, 0xcb777);
|
|
ppe_w32(ppe, MTK_PPE_SBW_CTRL, 0x7f);
|
|
}
|
|
--- a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c
|
|
+++ b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c
|
|
@@ -193,7 +193,7 @@ mtk_flow_set_output_device(struct mtk_et
|
|
if (mtk_flow_get_wdma_info(dev, dest_mac, &info) == 0) {
|
|
mtk_foe_entry_set_wdma(eth, foe, info.wdma_idx, info.queue,
|
|
info.bss, info.wcid);
|
|
- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
|
|
+ if (mtk_is_netsys_v2_or_greater(eth)) {
|
|
switch (info.wdma_idx) {
|
|
case 0:
|
|
pse_port = 8;
|
|
--- a/drivers/net/ethernet/mediatek/mtk_wed.c
|
|
+++ b/drivers/net/ethernet/mediatek/mtk_wed.c
|
|
@@ -1084,7 +1084,7 @@ mtk_wed_rx_reset(struct mtk_wed_device *
|
|
} else {
|
|
struct mtk_eth *eth = dev->hw->eth;
|
|
|
|
- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
|
|
+ if (mtk_is_netsys_v2_or_greater(eth))
|
|
wed_set(dev, MTK_WED_RESET_IDX,
|
|
MTK_WED_RESET_IDX_RX_V2);
|
|
else
|
|
@@ -1806,7 +1806,7 @@ void mtk_wed_add_hw(struct device_node *
|
|
hw->wdma = wdma;
|
|
hw->index = index;
|
|
hw->irq = irq;
|
|
- hw->version = MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) ? 2 : 1;
|
|
+ hw->version = mtk_is_netsys_v1(eth) ? 1 : 2;
|
|
|
|
if (hw->version == 1) {
|
|
hw->mirror = syscon_regmap_lookup_by_phandle(eth_np,
|