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mirror of https://git.openwrt.org/openwrt/openwrt.git synced 2024-10-19 14:08:17 +02:00

ipq806x: disable i2c device on gsbi4

Patch cherry-picked from the following location:
https://chromium-review.googlesource.com/#/c/269931/

Disable the i2c device on gsbi4 and mark gsbi4_h and gsbi4_qup clks as
unused. If they are enabled, clock framework will turn them off at end
of probe. On ipq806x by design gsbi4_qup, gsbi4_h clks and i2c on gsbi4
are meant for RPM usage. So turning them off in kernel is incorrect.

Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>

SVN-Revision: 45728
This commit is contained in:
John Crispin 2015-05-23 15:27:45 +00:00
parent 1c6d332d8f
commit f74477de48
7 changed files with 113 additions and 7 deletions

@ -0,0 +1,53 @@
--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
@@ -46,15 +46,12 @@
serial@16340000 {
status = "ok";
};
-
- i2c4: i2c@16380000 {
- status = "ok";
-
- clock-frequency = <200000>;
-
- pinctrl-0 = <&i2c4_pins>;
- pinctrl-names = "default";
- };
+ /*
+ * The i2c device on gsbi4 should not be enabled.
+ * On ipq806x designs gsbi4 i2c is meant for exclusive
+ * RPM usage. Turning this on in kernel manifests as
+ * i2c failure for the RPM.
+ */
};
gsbi5: gsbi@1a200000 {
--- a/drivers/clk/qcom/gcc-ipq806x.c
+++ b/drivers/clk/qcom/gcc-ipq806x.c
@@ -794,7 +794,7 @@ static struct clk_rcg gsbi7_qup_src = {
.parent_names = gcc_pxo_pll8,
.num_parents = 2,
.ops = &clk_rcg_ops,
- .flags = CLK_SET_PARENT_GATE,
+ .flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED,
},
},
};
@@ -810,7 +810,7 @@ static struct clk_branch gsbi7_qup_clk =
.parent_names = (const char *[]){ "gsbi7_qup_src" },
.num_parents = 1,
.ops = &clk_branch_ops,
- .flags = CLK_SET_RATE_PARENT,
+ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
},
},
};
@@ -858,7 +858,7 @@ static struct clk_branch gsbi4_h_clk = {
.hw.init = &(struct clk_init_data){
.name = "gsbi4_h_clk",
.ops = &clk_branch_ops,
- .flags = CLK_IS_ROOT,
+ .flags = CLK_IS_ROOT | CLK_IGNORE_UNUSED,
},
},
};

@ -1,6 +1,6 @@
--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
@@ -112,5 +112,29 @@
@@ -109,5 +109,29 @@
sata@29000000 {
status = "ok";
};

@ -38,7 +38,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
spi_pins: spi_pins {
mux {
pins = "gpio18", "gpio19", "gpio21";
@@ -136,5 +152,19 @@
@@ -133,5 +149,19 @@
usb30@1 {
status = "ok";
};

@ -42,7 +42,7 @@
};
gsbi@16300000 {
@@ -92,6 +118,7 @@
@@ -89,6 +115,7 @@
#size-cells = <1>;
spi-max-frequency = <50000000>;
reg = <0>;
@ -50,7 +50,7 @@
partition@0 {
label = "lowlevel_init";
@@ -166,5 +193,66 @@
@@ -163,5 +190,66 @@
pinctrl-0 = <&pcie2_pins>;
pinctrl-names = "default";
};

@ -0,0 +1,53 @@
--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
@@ -46,15 +46,12 @@
serial@16340000 {
status = "ok";
};
-
- i2c4: i2c@16380000 {
- status = "ok";
-
- clock-frequency = <200000>;
-
- pinctrl-0 = <&i2c4_pins>;
- pinctrl-names = "default";
- };
+ /*
+ * The i2c device on gsbi4 should not be enabled.
+ * On ipq806x designs gsbi4 i2c is meant for exclusive
+ * RPM usage. Turning this on in kernel manifests as
+ * i2c failure for the RPM.
+ */
};
gsbi5: gsbi@1a200000 {
--- a/drivers/clk/qcom/gcc-ipq806x.c
+++ b/drivers/clk/qcom/gcc-ipq806x.c
@@ -805,7 +805,7 @@ static struct clk_rcg gsbi7_qup_src = {
.parent_names = gcc_pxo_pll8,
.num_parents = 2,
.ops = &clk_rcg_ops,
- .flags = CLK_SET_PARENT_GATE,
+ .flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED,
},
},
};
@@ -821,7 +821,7 @@ static struct clk_branch gsbi7_qup_clk =
.parent_names = (const char *[]){ "gsbi7_qup_src" },
.num_parents = 1,
.ops = &clk_branch_ops,
- .flags = CLK_SET_RATE_PARENT,
+ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
},
},
};
@@ -869,7 +869,7 @@ static struct clk_branch gsbi4_h_clk = {
.hw.init = &(struct clk_init_data){
.name = "gsbi4_h_clk",
.ops = &clk_branch_ops,
- .flags = CLK_IS_ROOT,
+ .flags = CLK_IS_ROOT | CLK_IGNORE_UNUSED,
},
},
};

@ -38,7 +38,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
spi_pins: spi_pins {
mux {
pins = "gpio18", "gpio19", "gpio21";
@@ -112,5 +128,19 @@
@@ -109,5 +125,19 @@
sata@29000000 {
status = "ok";
};

@ -42,7 +42,7 @@
};
gsbi@16300000 {
@@ -92,6 +118,7 @@
@@ -89,6 +115,7 @@
#size-cells = <1>;
spi-max-frequency = <50000000>;
reg = <0>;
@ -50,7 +50,7 @@
partition@0 {
label = "lowlevel_init";
@@ -142,5 +169,66 @@
@@ -139,5 +166,66 @@
pinctrl-0 = <&pcie2_pins>;
pinctrl-names = "default";
};