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mediatek: add driver for built-in 2.5G Ethernet PHY
Add driver for the built-in 2.5G Ethernet PHY found in the MT7988 SoC. To function the PHY also needs firmware files which have not yet been published via linux-firmware. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
This commit is contained in:
Daniel Golle
parent
987a0b2b30
commit
ef2a831dab
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// SPDX-License-Identifier: GPL-2.0+
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#include <linux/bitfield.h>
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#include <linux/firmware.h>
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#include <linux/module.h>
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#include <linux/nvmem-consumer.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/phy.h>
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#define MEDAITEK_2P5GE_PHY_DMB_FW "mediatek/mediatek-2p5ge-phy-dmb.bin"
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#define MEDIATEK_2P5GE_PHY_PMB_FW "mediatek/mediatek-2p5ge-phy-pmb.bin"
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#define MD32_EN_CFG 0x18
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#define MD32_EN BIT(0)
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#define BASE100T_STATUS_EXTEND 0x10
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#define BASE1000T_STATUS_EXTEND 0x11
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#define EXTEND_CTRL_AND_STATUS 0x16
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#define PHY_AUX_CTRL_STATUS 0x1d
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#define PHY_AUX_DPX_MASK GENMASK(5, 5)
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#define PHY_AUX_SPEED_MASK GENMASK(4, 2)
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/* Registers on MDIO_MMD_VEND1 */
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#define MTK_PHY_LINK_STATUS_MISC 0xa2
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#define MTK_PHY_FDX_ENABLE BIT(5)
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/* Registers on MDIO_MMD_VEND2 */
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#define MTK_PHY_LED0_ON_CTRL 0x24
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#define MTK_PHY_LED0_ON_LINK1000 BIT(0)
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#define MTK_PHY_LED0_ON_LINK100 BIT(1)
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#define MTK_PHY_LED0_ON_LINK10 BIT(2)
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#define MTK_PHY_LED0_ON_LINK2500 BIT(7)
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#define MTK_PHY_LED0_POLARITY BIT(14)
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#define MTK_PHY_LED1_ON_CTRL 0x26
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#define MTK_PHY_LED1_ON_FDX BIT(4)
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#define MTK_PHY_LED1_ON_HDX BIT(5)
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#define MTK_PHY_LED1_POLARITY BIT(14)
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enum {
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PHY_AUX_SPD_10 = 0,
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PHY_AUX_SPD_100,
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PHY_AUX_SPD_1000,
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PHY_AUX_SPD_2500,
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};
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static int mt798x_2p5ge_phy_config_init(struct phy_device *phydev)
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{
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int ret;
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int i;
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const struct firmware *fw;
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struct device *dev = &phydev->mdio.dev;
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struct device_node *np;
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void __iomem *dmb_addr;
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void __iomem *pmb_addr;
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void __iomem *mcucsr_base;
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u16 reg;
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struct pinctrl *pinctrl;
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np = of_find_compatible_node(NULL, NULL, "mediatek,2p5gphy-fw");
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if (!np)
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return -ENOENT;
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dmb_addr = of_iomap(np, 0);
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if (!dmb_addr)
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return -ENOMEM;
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pmb_addr = of_iomap(np, 1);
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if (!pmb_addr)
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return -ENOMEM;
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mcucsr_base = of_iomap(np, 2);
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if (!mcucsr_base)
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return -ENOMEM;
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ret = request_firmware(&fw, MEDAITEK_2P5GE_PHY_DMB_FW, dev);
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if (ret) {
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dev_err(dev, "failed to load firmware: %s, ret: %d\n",
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MEDAITEK_2P5GE_PHY_DMB_FW, ret);
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return ret;
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}
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for (i = 0; i < fw->size - 1; i += 4)
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writel(*((uint32_t *)(fw->data + i)), dmb_addr + i);
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release_firmware(fw);
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ret = request_firmware(&fw, MEDIATEK_2P5GE_PHY_PMB_FW, dev);
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if (ret) {
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dev_err(dev, "failed to load firmware: %s, ret: %d\n",
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MEDIATEK_2P5GE_PHY_PMB_FW, ret);
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return ret;
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}
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for (i = 0; i < fw->size - 1; i += 4)
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writel(*((uint32_t *)(fw->data + i)), pmb_addr + i);
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release_firmware(fw);
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reg = readw(mcucsr_base + MD32_EN_CFG);
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writew(reg | MD32_EN, mcucsr_base + MD32_EN_CFG);
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dev_dbg(dev, "Firmware loading/trigger ok.\n");
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/* Setup LED */
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phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL,
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MTK_PHY_LED0_POLARITY);
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phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL,
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MTK_PHY_LED0_ON_LINK10 |
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MTK_PHY_LED0_ON_LINK100 |
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MTK_PHY_LED0_ON_LINK1000 |
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MTK_PHY_LED0_ON_LINK2500);
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phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_ON_CTRL,
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MTK_PHY_LED1_ON_FDX | MTK_PHY_LED1_ON_HDX);
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pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "i2p5gbe-led");
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if (IS_ERR(pinctrl)) {
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dev_err(&phydev->mdio.dev, "Fail to set LED pins!\n");
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return PTR_ERR(pinctrl);
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}
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return 0;
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}
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static int mt798x_2p5ge_phy_config_aneg(struct phy_device *phydev)
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{
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bool changed = false;
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u32 adv;
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int ret;
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if (phydev->autoneg == AUTONEG_DISABLE) {
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/* Configure half duplex with genphy_setup_forced,
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* because genphy_c45_pma_setup_forced does not support.
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*/
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return phydev->duplex != DUPLEX_FULL
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? genphy_setup_forced(phydev)
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: genphy_c45_pma_setup_forced(phydev);
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}
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ret = genphy_c45_an_config_aneg(phydev);
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if (ret < 0)
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return ret;
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if (ret > 0)
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changed = true;
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adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
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ret = phy_modify_changed(phydev, MII_CTRL1000,
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ADVERTISE_1000FULL | ADVERTISE_1000HALF,
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adv);
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if (ret < 0)
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return ret;
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if (ret > 0)
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changed = true;
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return genphy_c45_check_and_restart_aneg(phydev, changed);
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}
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static int mt798x_2p5ge_phy_get_features(struct phy_device *phydev)
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{
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int ret;
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ret = genphy_read_abilities(phydev);
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if (ret)
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return ret;
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/* We don't support HDX at MAC layer on mt798x.
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* So mask phy's HDX capabilities, too.
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*/
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linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
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phydev->supported);
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linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
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phydev->supported);
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linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
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phydev->supported);
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linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
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phydev->supported);
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linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported);
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return 0;
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}
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static int mt798x_2p5ge_phy_read_status(struct phy_device *phydev)
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{
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int ret;
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ret = genphy_update_link(phydev);
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if (ret)
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return ret;
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phydev->speed = SPEED_UNKNOWN;
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phydev->duplex = DUPLEX_UNKNOWN;
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phydev->pause = 0;
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phydev->asym_pause = 0;
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if (!phydev->link)
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return 0;
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if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) {
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ret = genphy_c45_read_lpa(phydev);
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if (ret < 0)
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return ret;
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/* Read the link partner's 1G advertisement */
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ret = phy_read(phydev, MII_STAT1000);
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if (ret < 0)
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return ret;
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mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, ret);
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} else if (phydev->autoneg == AUTONEG_DISABLE) {
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linkmode_zero(phydev->lp_advertising);
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}
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ret = phy_read(phydev, PHY_AUX_CTRL_STATUS);
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if (ret < 0)
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return ret;
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switch (FIELD_GET(PHY_AUX_SPEED_MASK, ret)) {
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case PHY_AUX_SPD_10:
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phydev->speed = SPEED_10;
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break;
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case PHY_AUX_SPD_100:
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phydev->speed = SPEED_100;
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break;
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case PHY_AUX_SPD_1000:
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phydev->speed = SPEED_1000;
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break;
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case PHY_AUX_SPD_2500:
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phydev->speed = SPEED_2500;
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phydev->duplex = DUPLEX_FULL; /* 2.5G must be FDX */
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break;
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}
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ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LINK_STATUS_MISC);
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if (ret < 0)
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return ret;
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phydev->duplex = (ret & MTK_PHY_FDX_ENABLE) ? DUPLEX_FULL : DUPLEX_HALF;
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return 0;
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}
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static struct phy_driver mtk_gephy_driver[] = {
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{
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PHY_ID_MATCH_EXACT(0x00339c11),
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.name = "MediaTek MT798x 2.5GbE PHY",
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.config_init = mt798x_2p5ge_phy_config_init,
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.config_aneg = mt798x_2p5ge_phy_config_aneg,
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.get_features = mt798x_2p5ge_phy_get_features,
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.read_status = mt798x_2p5ge_phy_read_status,
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},
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};
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module_phy_driver(mtk_gephy_driver);
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static struct mdio_device_id __maybe_unused mtk_2p5ge_phy_tbl[] = {
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{ PHY_ID_MATCH_VENDOR(0x00339c00) },
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{ }
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};
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MODULE_DESCRIPTION("MediaTek 2.5Gb Ethernet PHY driver");
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MODULE_AUTHOR("SkyLake Huang <SkyLake.Huang@mediatek.com>");
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MODULE_LICENSE("GPL");
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MODULE_DEVICE_TABLE(mdio, mtk_2p5ge_phy_tbl);
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MODULE_FIRMWARE(MEDAITEK_2P5GE_PHY_DMB_FW);
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MODULE_FIRMWARE(MEDIATEK_2P5GE_PHY_PMB_FW);
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@ -204,6 +204,7 @@ CONFIG_MAXLINEAR_GPHY=y
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CONFIG_MDIO_BUS=y
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CONFIG_MDIO_DEVICE=y
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CONFIG_MDIO_DEVRES=y
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CONFIG_MEDIATEK_2P5G_PHY=y
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CONFIG_MEDIATEK_GE_PHY=y
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CONFIG_MEDIATEK_GE_SOC_PHY=y
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CONFIG_MEDIATEK_WATCHDOG=y
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@ -225,6 +225,7 @@ CONFIG_MAGIC_SYSRQ=y
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CONFIG_MDIO_BUS=y
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CONFIG_MDIO_DEVICE=y
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CONFIG_MDIO_DEVRES=y
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# CONFIG_MEDIATEK_2P5G_PHY is not set
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CONFIG_MEDIATEK_GE_PHY=y
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# CONFIG_MEDIATEK_GE_SOC_PHY is not set
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CONFIG_MEDIATEK_WATCHDOG=y
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39
target/linux/mediatek/patches-5.15/732-net-phy-add-driver-for-MediaTek-2.5G-PHY.patch
Normal file
39
target/linux/mediatek/patches-5.15/732-net-phy-add-driver-for-MediaTek-2.5G-PHY.patch
Normal file
@ -0,0 +1,39 @@
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From 128dc09b0af36772062142ce9e85b19c84ac789a Mon Sep 17 00:00:00 2001
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From: Daniel Golle <daniel@makrotopia.org>
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Date: Tue, 28 Feb 2023 17:53:37 +0000
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Subject: [PATCH] net: phy: add driver for MediaTek 2.5G PHY
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Signed-off-by: Daniel Golle <daniel@makrotopia.org>
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---
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drivers/net/phy/Kconfig | 7 ++
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drivers/net/phy/Makefile | 1 +
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drivers/net/phy/mediatek-2p5ge.c | 220 +++++++++++++++++++++++++++++++
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3 files changed, 226 insertions(+)
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create mode 100644 drivers/net/phy/mediatek-2p5ge.c
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--- a/drivers/net/phy/Kconfig
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+++ b/drivers/net/phy/Kconfig
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@@ -304,6 +304,13 @@ config MEDIATEK_GE_SOC_PHY
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present in the SoCs efuse and will dynamically calibrate VCM
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(common-mode voltage) during startup.
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+config MEDIATEK_2P5G_PHY
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+ tristate "MediaTek 2.5G Ethernet PHY"
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+ depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
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+ default NET_MEDIATEK_SOC
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+ help
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+ Supports the MediaTek 2.5G Ethernet PHY.
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+
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config MICREL_PHY
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tristate "Micrel PHYs"
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help
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--- a/drivers/net/phy/Makefile
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+++ b/drivers/net/phy/Makefile
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@@ -80,6 +80,7 @@ obj-$(CONFIG_MARVELL_10G_PHY) += marvell
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obj-$(CONFIG_MARVELL_PHY) += marvell.o
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obj-$(CONFIG_MARVELL_88X2222_PHY) += marvell-88x2222.o
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obj-$(CONFIG_MAXLINEAR_GPHY) += mxl-gpy.o
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+obj-$(CONFIG_MEDIATEK_2P5G_PHY) += mediatek-2p5ge.o
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obj-$(CONFIG_MEDIATEK_GE_PHY) += mediatek-ge.o
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obj-$(CONFIG_MEDIATEK_GE_SOC_PHY) += mediatek-ge-soc.o
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obj-$(CONFIG_MESON_GXL_PHY) += meson-gxl.o
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