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Code Issues

kernel: bump 5.4 to 5.4.45

Browse Source 
Fixes CVE-2020-10757 via upstream commit df4988aa1c96 ("mm: Fix mremap
not considering huge pmd devmap").

Resolved merge conflict in the following patches:

 bcm27xx: 950-0128-gpiolib-Don-t-prevent-IRQ-usage-of-output-GPIOs.patch

Refreshed patches, removed upstreamed patch:

 generic: 751-v5.8-net-dsa-mt7530-set-CPU-port-to-fallback-mode.patch
 generic: 754-v5.7-net-dsa-mt7530-fix-roaming-from-DSA-user-ports.patch

Run tested: qemu-x86-64
Build tested: x86/64, imx6, sunxi/a53

Signed-off-by: Petr Štetiar <ynezz@true.cz>
This commit is contained in:
Petr Štetiar 2020-06-09 14:18:25 +02:00
parent df6a33a8d4
commit e5aa498acb
30 changed files with 352 additions and 596 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
include/kernel-version.mk
View File

@ -8,11 +8,11 @@ endif
LINUX_VERSION-4.14 = .180
LINUX_VERSION-4.19 = .123
LINUX_VERSION-5.4 = .43
LINUX_VERSION-5.4 = .45
LINUX_KERNEL_HASH-4.14.180 = 444ef973d9b6a6ea174e4a9086f0aea980d8575d13302e431ad688f22e27ed0e
LINUX_KERNEL_HASH-4.19.123 = a79914d31a8d8c6b0e2bb0f2b143d615fe8a6c4dd2e0f36e97aa20efd69a993f
LINUX_KERNEL_HASH-5.4.43 = 2667b90a42d42557aca9e3d37bba1b4e71809b9523958e6870ada311c4790744
LINUX_KERNEL_HASH-5.4.45 = 103f039f34a9009c42ea643b4f473bda6bb9607d5ad7f63b56b3e2351615fe2e
remove_uri_prefix=$(subst git://,,$(subst http://,,$(subst https://,,$(1))))
sanitize_uri=$(call qstrip,$(subst @,_,$(subst :,_,$(subst .,_,$(subst -,_,$(subst /,_,$(1)))))))

10
target/linux/bcm27xx/patches-5.4/950-0128-gpiolib-Don-t-prevent-IRQ-usage-of-output-GPIOs.patch
View File

@ -37,12 +37,14 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org>
gpiod_err(desc,
"%s: tried to set a GPIO tied to an IRQ as output\n",
__func__);
@@ -3894,7 +3896,7 @@ int gpiochip_lock_as_irq(struct gpio_chi
}
@@ -3895,8 +3897,8 @@ int gpiochip_lock_as_irq(struct gpio_chi
}
- if (test_bit(FLAG_IS_OUT, &desc->flags)) {
+ if (dont_test_bit(FLAG_IS_OUT, &desc->flags)) {
/* To be valid for IRQ the line needs to be input or open drain */
- if (test_bit(FLAG_IS_OUT, &desc->flags) &&
- !test_bit(FLAG_OPEN_DRAIN, &desc->flags)) {
+ if (dont_test_bit(FLAG_IS_OUT, &desc->flags) &&
+ !dont_test_bit(FLAG_OPEN_DRAIN, &desc->flags)) {
chip_err(chip,
"%s: tried to flag a GPIO set as output for IRQ\n",
__func__);

2
target/linux/bcm53xx/patches-5.4/700-b53-add-hacky-CPU-port-fixes-for-devices-not-using-p.patch
View File

@ -21,7 +21,7 @@ Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
#include "b53_regs.h"
#include "b53_priv.h"
@@ -1579,6 +1580,28 @@ static int b53_switch_init(struct b53_de
@@ -1587,6 +1588,28 @@ static int b53_switch_init(struct b53_de
return ret;
}

8
target/linux/generic/backport-5.4/745-v5.7-net-dsa-mt7530-add-support-for-port-mirroring.patch
View File

@ -17,7 +17,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
@@ -1151,6 +1151,64 @@ mt7530_port_vlan_del(struct dsa_switch *
@@ -1153,6 +1153,64 @@ mt7530_port_vlan_del(struct dsa_switch *
return 0;
}
@ -93,7 +93,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
.phylink_mac_config = mt7530_phylink_mac_config,
--- a/drivers/net/dsa/mt7530.h
+++ b/drivers/net/dsa/mt7530.h
@@ -36,6 +36,9 @@ enum {
@@ -37,6 +37,9 @@ enum {
#define CPU_EN BIT(7)
#define CPU_PORT(x) ((x) << 4)
#define CPU_MASK (0xf << 4)
@ -103,7 +103,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
/* Registers for address table access */
#define MT7530_ATA1 0x74
@@ -141,6 +144,8 @@ enum mt7530_stp_state {
@@ -142,6 +145,8 @@ enum mt7530_stp_state {
/* Register for port control */
#define MT7530_PCR_P(x) (0x2004 + ((x) * 0x100))
@ -112,7 +112,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
#define PORT_VLAN(x) ((x) & 0x3)
enum mt7530_port_mode {
@@ -457,6 +462,8 @@ struct mt7530_priv {
@@ -464,6 +469,8 @@ struct mt7530_priv {
phy_interface_t p6_interface;
phy_interface_t p5_interface;
unsigned int p5_intf_sel;

65
target/linux/generic/backport-5.4/751-v5.8-net-dsa-mt7530-set-CPU-port-to-fallback-mode.patch
View File

@ -1,65 +0,0 @@
From 38152ea37d8bdaffa22603e0a5b5b86cfa8714c9 Mon Sep 17 00:00:00 2001
From: DENG Qingfang <dqfext@gmail.com>
Date: Wed, 13 May 2020 23:37:17 +0800
Subject: net: dsa: mt7530: set CPU port to fallback mode
Currently, setting a bridge's self PVID to other value and deleting
the default VID 1 renders untagged ports of that VLAN unable to talk to
the CPU port:
bridge vlan add dev br0 vid 2 pvid untagged self
bridge vlan del dev br0 vid 1 self
bridge vlan add dev sw0p0 vid 2 pvid untagged
bridge vlan del dev sw0p0 vid 1
# br0 cannot send untagged frames out of sw0p0 anymore
That is because the CPU port is set to security mode and its PVID is
still 1, and untagged frames are dropped due to VLAN member violation.
Set the CPU port to fallback mode so untagged frames can pass through.
Fixes: 83163f7dca56 ("net: dsa: mediatek: add VLAN support for MT7530")
Signed-off-by: DENG Qingfang <dqfext@gmail.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
drivers/net/dsa/mt7530.c | 11 ++++++++---
drivers/net/dsa/mt7530.h | 6 ++++++
2 files changed, 14 insertions(+), 3 deletions(-)
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
@@ -821,10 +821,15 @@ mt7530_port_set_vlan_aware(struct dsa_sw
PCR_MATRIX_MASK, PCR_MATRIX(MT7530_ALL_MEMBERS));
/* Trapped into security mode allows packet forwarding through VLAN
- * table lookup.
+ * table lookup. CPU port is set to fallback mode to let untagged
+ * frames pass through.
*/
- mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
- MT7530_PORT_SECURITY_MODE);
+ if (dsa_is_cpu_port(ds, port))
+ mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
+ MT7530_PORT_FALLBACK_MODE);
+ else
+ mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
+ MT7530_PORT_SECURITY_MODE);
/* Set the port as a user port which is to be able to recognize VID
* from incoming packets before fetching entry within the VLAN table.
--- a/drivers/net/dsa/mt7530.h
+++ b/drivers/net/dsa/mt7530.h
@@ -152,6 +152,12 @@ enum mt7530_port_mode {
/* Port Matrix Mode: Frames are forwarded by the PCR_MATRIX members. */
MT7530_PORT_MATRIX_MODE = PORT_VLAN(0),
+ /* Fallback Mode: Forward received frames with ingress ports that do
+ * not belong to the VLAN member. Frames whose VID is not listed on
+ * the VLAN table are forwarded by the PCR_MATRIX members.
+ */
+ MT7530_PORT_FALLBACK_MODE = PORT_VLAN(1),
+
/* Security Mode: Discard any frame due to ingress membership
* violation or VID missed on the VLAN table.
*/

6
target/linux/generic/backport-5.4/753-v5.8-net-dsa-mt7530-fix-VLAN-setup.patch
View File

@ -15,7 +15,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
@@ -1096,12 +1096,6 @@ mt7530_port_vlan_add(struct dsa_switch *
@@ -1093,12 +1093,6 @@ mt7530_port_vlan_add(struct dsa_switch *
struct mt7530_priv *priv = ds->priv;
u16 vid;
@ -28,7 +28,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
mutex_lock(&priv->reg_mutex);
for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
@@ -1127,12 +1121,6 @@ mt7530_port_vlan_del(struct dsa_switch *
@@ -1124,12 +1118,6 @@ mt7530_port_vlan_del(struct dsa_switch *
struct mt7530_priv *priv = ds->priv;
u16 vid, pvid;
@ -41,7 +41,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
mutex_lock(&priv->reg_mutex);
pvid = priv->ports[port].pvid;
@@ -1245,6 +1233,7 @@ mt7530_setup(struct dsa_switch *ds)
@@ -1242,6 +1230,7 @@ mt7530_setup(struct dsa_switch *ds)
* as two netdev instances.
*/
dn = ds->ports[MT7530_CPU_PORT].master->dev.of_node->parent;

116
target/linux/generic/backport-5.4/754-v5.7-net-dsa-mt7530-fix-roaming-from-DSA-user-ports.patch
View File

@ -1,116 +0,0 @@
From 5e5502e012b8129e11be616acb0f9c34bc8f8adb Mon Sep 17 00:00:00 2001
From: DENG Qingfang <dqfext@gmail.com>
Date: Wed, 13 May 2020 23:10:16 +0800
Subject: net: dsa: mt7530: fix roaming from DSA user ports
When a client moves from a DSA user port to a software port in a bridge,
it cannot reach any other clients that connected to the DSA user ports.
That is because SA learning on the CPU port is disabled, so the switch
ignores the client's frames from the CPU port and still thinks it is at
the user port.
Fix it by enabling SA learning on the CPU port.
To prevent the switch from learning from flooding frames from the CPU
port, set skb->offload_fwd_mark to 1 for unicast and broadcast frames,
and let the switch flood them instead of trapping to the CPU port.
Multicast frames still need to be trapped to the CPU port for snooping,
so set the SA_DIS bit of the MTK tag to 1 when transmitting those frames
to disable SA learning.
Fixes: b8f126a8d543 ("net-next: dsa: add dsa support for Mediatek MT7530 switch")
Signed-off-by: DENG Qingfang <dqfext@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
drivers/net/dsa/mt7530.c | 9 ++-------
drivers/net/dsa/mt7530.h | 1 +
net/dsa/tag_mtk.c | 15 +++++++++++++++
3 files changed, 18 insertions(+), 7 deletions(-)
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
@@ -639,11 +639,8 @@ mt7530_cpu_port_enable(struct mt7530_pri
mt7530_write(priv, MT7530_PVC_P(port),
PORT_SPEC_TAG);
- /* Disable auto learning on the cpu port */
- mt7530_set(priv, MT7530_PSC_P(port), SA_DIS);
-
- /* Unknown unicast frame fordwarding to the cpu port */
- mt7530_set(priv, MT7530_MFC, UNU_FFP(BIT(port)));
+ /* Unknown multicast frame forwarding to the cpu port */
+ mt7530_rmw(priv, MT7530_MFC, UNM_FFP_MASK, UNM_FFP(BIT(port)));
/* Set CPU port number */
if (priv->id == ID_MT7621)
@@ -1298,8 +1295,6 @@ mt7530_setup(struct dsa_switch *ds)
/* Enable and reset MIB counters */
mt7530_mib_reset(ds);
- mt7530_clear(priv, MT7530_MFC, UNU_FFP_MASK);
-
for (i = 0; i < MT7530_NUM_PORTS; i++) {
/* Disable forwarding by default on all ports */
mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
--- a/drivers/net/dsa/mt7530.h
+++ b/drivers/net/dsa/mt7530.h
@@ -31,6 +31,7 @@ enum {
#define MT7530_MFC 0x10
#define BC_FFP(x) (((x) & 0xff) << 24)
#define UNM_FFP(x) (((x) & 0xff) << 16)
+#define UNM_FFP_MASK UNM_FFP(~0)
#define UNU_FFP(x) (((x) & 0xff) << 8)
#define UNU_FFP_MASK UNU_FFP(~0)
#define CPU_EN BIT(7)
--- a/net/dsa/tag_mtk.c
+++ b/net/dsa/tag_mtk.c
@@ -15,6 +15,7 @@
#define MTK_HDR_XMIT_TAGGED_TPID_8100 1
#define MTK_HDR_RECV_SOURCE_PORT_MASK GENMASK(2, 0)
#define MTK_HDR_XMIT_DP_BIT_MASK GENMASK(5, 0)
+#define MTK_HDR_XMIT_SA_DIS BIT(6)
static struct sk_buff *mtk_tag_xmit(struct sk_buff *skb,
struct net_device *dev)
@@ -22,6 +23,9 @@ static struct sk_buff *mtk_tag_xmit(stru
struct dsa_port *dp = dsa_slave_to_port(dev);
u8 *mtk_tag;
bool is_vlan_skb = true;
+ unsigned char *dest = eth_hdr(skb)->h_dest;
+ bool is_multicast_skb = is_multicast_ether_addr(dest) &&
+ !is_broadcast_ether_addr(dest);
/* Build the special tag after the MAC Source Address. If VLAN header
* is present, it's required that VLAN header and special tag is
@@ -47,6 +51,10 @@ static struct sk_buff *mtk_tag_xmit(stru
MTK_HDR_XMIT_UNTAGGED;
mtk_tag[1] = (1 << dp->index) & MTK_HDR_XMIT_DP_BIT_MASK;
+ /* Disable SA learning for multicast frames */
+ if (unlikely(is_multicast_skb))
+ mtk_tag[1] |= MTK_HDR_XMIT_SA_DIS;
+
/* Tag control information is kept for 802.1Q */
if (!is_vlan_skb) {
mtk_tag[2] = 0;
@@ -61,6 +69,9 @@ static struct sk_buff *mtk_tag_rcv(struc
{
int port;
__be16 *phdr, hdr;
+ unsigned char *dest = eth_hdr(skb)->h_dest;
+ bool is_multicast_skb = is_multicast_ether_addr(dest) &&
+ !is_broadcast_ether_addr(dest);
if (unlikely(!pskb_may_pull(skb, MTK_HDR_LEN)))
return NULL;
@@ -86,6 +97,10 @@ static struct sk_buff *mtk_tag_rcv(struc
if (!skb->dev)
return NULL;
+ /* Only unicast or broadcast frames are offloaded */
+ if (likely(!is_multicast_skb))
+ skb->offload_fwd_mark = 1;
+
return skb;
}

4
target/linux/generic/pending-5.4/332-arc-add-OWRTDTB-section.patch
View File

@ -42,7 +42,7 @@ Signed-off-by: Evgeniy Didin <Evgeniy.Didin@synopsys.com>
;----------------------------------------------------------------
--- a/arch/arc/kernel/setup.c
+++ b/arch/arc/kernel/setup.c
@@ -491,6 +491,8 @@ static inline bool uboot_arg_invalid(uns
@@ -492,6 +492,8 @@ static inline bool uboot_arg_invalid(uns
/* We always pass 0 as magic from U-boot */
#define UBOOT_MAGIC_VALUE 0
@ -51,7 +51,7 @@ Signed-off-by: Evgeniy Didin <Evgeniy.Didin@synopsys.com>
void __init handle_uboot_args(void)
{
bool use_embedded_dtb = true;
@@ -529,7 +531,7 @@ void __init handle_uboot_args(void)
@@ -530,7 +532,7 @@ void __init handle_uboot_args(void)
ignore_uboot_args:
if (use_embedded_dtb) {

10
target/linux/generic/pending-5.4/680-NET-skip-GRO-for-foreign-MAC-addresses.patch
View File

@ -32,7 +32,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
__u16 tc_index; /* traffic control index */
--- a/net/core/dev.c
+++ b/net/core/dev.c
@@ -5461,6 +5461,9 @@ static enum gro_result dev_gro_receive(s
@@ -5471,6 +5471,9 @@ static enum gro_result dev_gro_receive(s
int same_flow;
int grow;
@ -42,7 +42,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
if (netif_elide_gro(skb->dev))
goto normal;
@@ -7254,6 +7257,48 @@ static void __netdev_adjacent_dev_unlink
@@ -7264,6 +7267,48 @@ static void __netdev_adjacent_dev_unlink
&upper_dev->adj_list.lower);
}
@ -91,7 +91,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
static int __netdev_upper_dev_link(struct net_device *dev,
struct net_device *upper_dev, bool master,
void *upper_priv, void *upper_info,
@@ -7304,6 +7349,7 @@ static int __netdev_upper_dev_link(struc
@@ -7314,6 +7359,7 @@ static int __netdev_upper_dev_link(struc
if (ret)
return ret;
@ -99,7 +99,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
ret = call_netdevice_notifiers_info(NETDEV_CHANGEUPPER,
&changeupper_info.info);
ret = notifier_to_errno(ret);
@@ -7397,6 +7443,7 @@ void netdev_upper_dev_unlink(struct net_
@@ -7407,6 +7453,7 @@ void netdev_upper_dev_unlink(struct net_
__netdev_adjacent_dev_unlink_neighbour(dev, upper_dev);
@ -107,7 +107,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
call_netdevice_notifiers_info(NETDEV_CHANGEUPPER,
&changeupper_info.info);
@@ -8127,6 +8174,7 @@ int dev_set_mac_address(struct net_devic
@@ -8137,6 +8184,7 @@ int dev_set_mac_address(struct net_devic
if (err)
return err;
dev->addr_assign_type = NET_ADDR_SET;

9
target/linux/imx6/patches-5.4/006-v5.7-ARM-dts-imx-ventana-add-fxos8700-on-gateworks-boards.patch
View File

@ -13,8 +13,6 @@ Signed-off-by: Shawn Guo <shawnguo@kernel.org>
arch/arm/boot/dts/imx6qdl-gw54xx.dtsi | 5 +++++
3 files changed, 15 insertions(+)
diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
index 1a9a9d9..60563ff 100644
--- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
@@ -313,6 +313,11 @@
@ -29,8 +27,6 @@ index 1a9a9d9..60563ff 100644
};
&ldb {
diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
index 54b2bea..8942bec 100644
--- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
@@ -304,6 +304,11 @@
@ -45,8 +41,6 @@ index 54b2bea..8942bec 100644
};
&ldb {
diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
index 1b6c133..c40583d 100644
--- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
@@ -361,6 +361,11 @@
@ -61,6 +55,3 @@ index 1b6c133..c40583d 100644
};
&ldb {
--
2.7.4

5
target/linux/imx6/patches-5.4/006-v5.7-ARM-dts-imx6qdl-gw5910-add-CC1352-UART.patch
View File

@ -11,8 +11,6 @@ Signed-off-by: Shawn Guo <shawnguo@kernel.org>
arch/arm/boot/dts/imx6qdl-gw5910.dtsi | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/arm/boot/dts/imx6qdl-gw5910.dtsi b/arch/arm/boot/dts/imx6qdl-gw5910.dtsi
index be1af74..30fe47f 100644
--- a/arch/arm/boot/dts/imx6qdl-gw5910.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw5910.dtsi
@@ -220,6 +220,14 @@
@ -54,6 +52,3 @@ index be1af74..30fe47f 100644
pinctrl_uart4: uart4grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
--
2.7.4

5
target/linux/imx6/patches-5.4/006-v5.8-ARM-dts-imx6qdl-gw552x-add-USB-OTG-support.patch
View File

@ -13,8 +13,6 @@ Signed-off-by: Shawn Guo <shawnguo@kernel.org>
arch/arm/boot/dts/imx6qdl-gw552x.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi
index dc646b7..bb35971 100644
--- a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi
@@ -258,6 +258,14 @@
@ -45,6 +43,3 @@ index dc646b7..bb35971 100644
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
--
2.7.4

5
target/linux/imx6/patches-5.4/007-v5.8-ARM-dts-imx6qdl-gw560x-add-lsm9ds1-iio-imu-magn-supp.patch
View File

@ -13,8 +13,6 @@ Signed-off-by: Shawn Guo <shawnguo@kernel.org>
arch/arm/boot/dts/imx6qdl-gw560x.dtsi | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/arch/arm/boot/dts/imx6qdl-gw560x.dtsi b/arch/arm/boot/dts/imx6qdl-gw560x.dtsi
index e8e36df..69ca70d 100644
--- a/arch/arm/boot/dts/imx6qdl-gw560x.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw560x.dtsi
@@ -295,6 +295,15 @@
@ -76,6 +74,3 @@ index e8e36df..69ca70d 100644
pinctrl_pcie: pciegrp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x1b0b0 /* PCI_RST# */
--
2.7.4

5
target/linux/imx6/patches-5.4/008-v5.8-ARM-dts-imx6qdl-gw5904-add-lsm9ds1-iio-imu-magn-supp.patch
View File

@ -13,8 +13,6 @@ Signed-off-by: Shawn Guo <shawnguo@kernel.org>
arch/arm/boot/dts/imx6qdl-gw5904.dtsi | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/arch/arm/boot/dts/imx6qdl-gw5904.dtsi b/arch/arm/boot/dts/imx6qdl-gw5904.dtsi
index 6d21cc6..76d6cf5 100644
--- a/arch/arm/boot/dts/imx6qdl-gw5904.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw5904.dtsi
@@ -248,6 +248,15 @@
@ -69,6 +67,3 @@ index 6d21cc6..76d6cf5 100644
pinctrl_pcie: pciegrp {
fsl,pins = <
MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* PCIE RST */
--
2.7.4

5
target/linux/imx6/patches-5.4/009-v5.8-ARM-dts-imx6qdl-gw5910-add-support-for-bcm4330-bt.patch
View File

@ -16,8 +16,6 @@ Signed-off-by: Shawn Guo <shawnguo@kernel.org>
arch/arm/boot/dts/imx6qdl-gw5910.dtsi | 32 ++++++++++++--------------------
1 file changed, 12 insertions(+), 20 deletions(-)
diff --git a/arch/arm/boot/dts/imx6qdl-gw5910.dtsi b/arch/arm/boot/dts/imx6qdl-gw5910.dtsi
index 30fe47f..b850f8f 100644
--- a/arch/arm/boot/dts/imx6qdl-gw5910.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw5910.dtsi
@@ -83,19 +83,6 @@
@ -82,6 +80,3 @@ index 30fe47f..b850f8f 100644
pinctrl_reg_wl: regwlgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b1
--
2.7.4

5
target/linux/imx6/patches-5.4/010-v5.8-ARM-dts-imx6qdl-gw5910-fix-wlan-regulator.patch
View File

@ -12,8 +12,6 @@ Signed-off-by: Shawn Guo <shawnguo@kernel.org>
arch/arm/boot/dts/imx6qdl-gw5910.dtsi | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/imx6qdl-gw5910.dtsi b/arch/arm/boot/dts/imx6qdl-gw5910.dtsi
index b850f8f..0857de5 100644
--- a/arch/arm/boot/dts/imx6qdl-gw5910.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw5910.dtsi
@@ -81,7 +81,6 @@
@ -33,6 +31,3 @@ index b850f8f..0857de5 100644
non-removable;
bus-width = <4>;
status = "okay";
--
2.7.4

2
target/linux/layerscape/patches-5.4/701-net-0122-config-enable-SDK-FMan-driver.patch
View File

@ -10,7 +10,7 @@ Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
--- a/drivers/net/ethernet/freescale/Kconfig
+++ b/drivers/net/ethernet/freescale/Kconfig
@@ -95,6 +95,7 @@ config GIANFAR
@@ -97,6 +97,7 @@ config GIANFAR
This driver supports the Gigabit TSEC on the MPC83xx, MPC85xx,
and MPC86xx family of chips, the eTSEC on LS1021A and the FEC
on the 8540.

2
target/linux/layerscape/patches-5.4/701-net-0123-config-enable-SDK-DPAA-driver.patch
View File

@ -10,7 +10,7 @@ Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
--- a/drivers/net/ethernet/freescale/Kconfig
+++ b/drivers/net/ethernet/freescale/Kconfig
@@ -96,7 +96,7 @@ config GIANFAR
@@ -98,7 +98,7 @@ config GIANFAR
and MPC86xx family of chips, the eTSEC on LS1021A and the FEC
on the 8540.
source "drivers/net/ethernet/freescale/sdk_fman/Kconfig"

2
target/linux/layerscape/patches-5.4/701-net-0273-net-dsa-ocelot-add-tsn-support-for-felix-switch.patch
View File

@ -648,7 +648,7 @@ Signed-off-by: Xiaoliang Yang <xiaoliang.yang_1@nxp.com>
static const u32 vsc9959_gcb_regmap[] = {
--- a/include/net/dsa.h
+++ b/include/net/dsa.h
@@ -545,6 +545,7 @@ struct dsa_switch_ops {
@@ -552,6 +552,7 @@ struct dsa_switch_ops {
*/
netdev_tx_t (*port_deferred_xmit)(struct dsa_switch *ds, int port,
struct sk_buff *skb);

4
target/linux/layerscape/patches-5.4/701-net-0381-net-dsa-Pass-pcs_poll-flag-from-driver-to-PHYLINK.patch
View File

@ -24,7 +24,7 @@ on touch") which was merged in v5.4-rc3.
--- a/include/net/dsa.h
+++ b/include/net/dsa.h
@@ -277,6 +277,11 @@ struct dsa_switch {
@@ -284,6 +284,11 @@ struct dsa_switch {
*/
bool vlan_filtering;
@ -38,7 +38,7 @@ on touch") which was merged in v5.4-rc3.
struct dsa_port ports[];
--- a/net/dsa/port.c
+++ b/net/dsa/port.c
@@ -625,6 +625,7 @@ static int dsa_port_phylink_register(str
@@ -639,6 +639,7 @@ static int dsa_port_phylink_register(str
dp->pl_config.dev = ds->dev;
dp->pl_config.type = PHYLINK_DEV;

2
target/linux/layerscape/patches-5.4/814-qe-0006-config-qe-add-irq-qeic-support.patch
View File

@ -58,4 +58,4 @@ Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
+ depends on QUICC_ENGINE && FSL_SOC && PPC32
select FSL_PQ_MDIO
select PHYLIB
---help---
select FIXED_PHY

268
target/linux/mediatek/patches-5.4/0500-v5.6-crypto-backport-inside-secure.patch
View File

@ -1,6 +1,6 @@
--- a/drivers/crypto/inside-secure/safexcel.c
+++ b/drivers/crypto/inside-secure/safexcel.c
@@ -75,9 +75,9 @@
@@ -75,9 +75,9 @@ static void eip197_trc_cache_banksel(str
}
static u32 eip197_trc_cache_probe(struct safexcel_crypto_priv *priv,
@ -12,7 +12,7 @@
int actbank;
/*
@@ -87,32 +87,37 @@
@@ -87,32 +87,37 @@ static u32 eip197_trc_cache_probe(struct
addrhi = 1 << (16 + maxbanks);
addrlo = 0;
actbank = min(maxbanks - 1, 0);
@ -60,7 +60,7 @@
}
return addrhi;
}
@@ -150,7 +155,7 @@
@@ -150,7 +155,7 @@ static void eip197_trc_cache_clear(struc
htable_offset + i * sizeof(u32));
}
@ -69,7 +69,7 @@
{
u32 val, dsize, asize;
int cs_rc_max, cs_ht_wc, cs_trc_rec_wc, cs_trc_lg_rec_wc;
@@ -183,7 +188,7 @@
@@ -183,7 +188,7 @@ static void eip197_trc_cache_init(struct
writel(val, priv->base + EIP197_TRC_PARAMS);
/* Probed data RAM size in bytes */
@ -78,7 +78,7 @@
/*
* Now probe the administration RAM size pretty much the same way
@@ -196,11 +201,18 @@
@@ -196,11 +201,18 @@ static void eip197_trc_cache_init(struct
writel(val, priv->base + EIP197_TRC_PARAMS);
/* Probed admin RAM size in admin words */
@ -98,7 +98,7 @@
/*
* Determine optimal configuration from RAM sizes
* Note that we assume that the physical RAM configuration is sane
@@ -251,6 +263,7 @@
@@ -251,6 +263,7 @@ static void eip197_trc_cache_init(struct
dev_info(priv->dev, "TRC init: %dd,%da (%dr,%dh)\n",
dsize, asize, cs_rc_max, cs_ht_wc + cs_ht_wc);
@ -106,7 +106,7 @@
}
static void eip197_init_firmware(struct safexcel_crypto_priv *priv)
@@ -298,13 +311,14 @@
@@ -298,13 +311,14 @@ static void eip197_init_firmware(struct
static int eip197_write_firmware(struct safexcel_crypto_priv *priv,
const struct firmware *fw)
{
@ -123,7 +123,7 @@
/* Exclude final 2 NOPs from size */
return i - EIP197_FW_TERMINAL_NOPS;
@@ -471,6 +485,14 @@
@@ -471,6 +485,14 @@ static int safexcel_hw_setup_cdesc_rings
cd_fetch_cnt = ((1 << priv->hwconfig.hwcfsize) /
cd_size_rnd) - 1;
}
@ -138,7 +138,7 @@
for (i = 0; i < priv->config.rings; i++) {
/* ring base address */
@@ -479,12 +501,12 @@
@@ -479,12 +501,12 @@ static int safexcel_hw_setup_cdesc_rings
writel(upper_32_bits(priv->ring[i].cdr.base_dma),
EIP197_HIA_CDR(priv, i) + EIP197_HIA_xDR_RING_BASE_ADDR_HI);
@ -154,7 +154,7 @@
EIP197_HIA_CDR(priv, i) + EIP197_HIA_xDR_CFG);
/* Configure DMA tx control */
@@ -527,13 +549,13 @@
@@ -527,13 +549,13 @@ static int safexcel_hw_setup_rdesc_rings
writel(upper_32_bits(priv->ring[i].rdr.base_dma),
EIP197_HIA_RDR(priv, i) + EIP197_HIA_xDR_RING_BASE_ADDR_HI);
@ -170,7 +170,7 @@
EIP197_HIA_RDR(priv, i) + EIP197_HIA_xDR_CFG);
/* Configure DMA tx control */
@@ -559,7 +581,7 @@
@@ -559,7 +581,7 @@ static int safexcel_hw_setup_rdesc_rings
static int safexcel_hw_init(struct safexcel_crypto_priv *priv)
{
u32 val;
@ -179,7 +179,7 @@
dev_dbg(priv->dev, "HW init: using %d pipe(s) and %d ring(s)\n",
priv->config.pes, priv->config.rings);
@@ -595,8 +617,8 @@
@@ -595,8 +617,8 @@ static int safexcel_hw_init(struct safex
writel(EIP197_DxE_THR_CTRL_RESET_PE,
EIP197_HIA_DFE_THR(priv) + EIP197_HIA_DFE_THR_CTRL(pe));
@ -190,7 +190,7 @@
writel(EIP197_HIA_RA_PE_CTRL_RESET,
EIP197_HIA_AIC(priv) + EIP197_HIA_RA_PE_CTRL(pe));
@@ -639,9 +661,16 @@
@@ -639,9 +661,16 @@ static int safexcel_hw_init(struct safex
;
/* DMA transfer size to use */
@ -209,7 +209,7 @@
val |= EIP197_HIA_DxE_CFG_DATA_CACHE_CTRL(WR_CACHE_3BITS);
val |= EIP197_HIA_DSE_CFG_ALWAYS_BUFFERABLE;
/* FIXME: instability issues can occur for EIP97 but disabling
@@ -655,8 +684,8 @@
@@ -655,8 +684,8 @@ static int safexcel_hw_init(struct safex
writel(0, EIP197_HIA_DSE_THR(priv) + EIP197_HIA_DSE_THR_CTRL(pe));
/* Configure the procesing engine thresholds */
@ -220,7 +220,7 @@
EIP197_PE(priv) + EIP197_PE_OUT_DBUF_THRES(pe));
/* Processing Engine configuration */
@@ -696,7 +725,7 @@
@@ -696,7 +725,7 @@ static int safexcel_hw_init(struct safex
writel(0,
EIP197_HIA_CDR(priv, i) + EIP197_HIA_xDR_PROC_PNTR);
@ -229,7 +229,7 @@
EIP197_HIA_CDR(priv, i) + EIP197_HIA_xDR_RING_SIZE);
}
@@ -719,7 +748,7 @@
@@ -719,7 +748,7 @@ static int safexcel_hw_init(struct safex
EIP197_HIA_RDR(priv, i) + EIP197_HIA_xDR_PROC_PNTR);
/* Ring size */
@ -238,7 +238,7 @@
EIP197_HIA_RDR(priv, i) + EIP197_HIA_xDR_RING_SIZE);
}
@@ -736,19 +765,28 @@
@@ -736,19 +765,28 @@ static int safexcel_hw_init(struct safex
/* Clear any HIA interrupt */
writel(GENMASK(30, 20), EIP197_HIA_AIC_G(priv) + EIP197_HIA_AIC_G_ACK);
@ -274,7 +274,7 @@
}
/* Called with ring's lock taken */
@@ -836,20 +874,24 @@
@@ -836,20 +874,24 @@ finalize:
spin_unlock_bh(&priv->ring[ring].lock);
/* let the RDR know we have pending descriptors */
@ -305,7 +305,7 @@
return 0;
if (rdesc->descriptor_overflow)
@@ -858,13 +900,14 @@
@@ -858,13 +900,14 @@ inline int safexcel_rdesc_check_errors(s
if (rdesc->buffer_overflow)
dev_err(priv->dev, "Buffer overflow detected");
@ -323,7 +323,7 @@
(BIT(7) | BIT(4) | BIT(3) | BIT(0))) {
/*
* Give priority over authentication fails:
@@ -872,7 +915,7 @@
@@ -872,7 +915,7 @@ inline int safexcel_rdesc_check_errors(s
* something wrong with the input!
*/
return -EINVAL;
@ -332,7 +332,7 @@
/* Authentication failed */
return -EBADMSG;
}
@@ -931,16 +974,18 @@
@@ -931,16 +974,18 @@ int safexcel_invalidate_cache(struct cry
{
struct safexcel_command_desc *cdesc;
struct safexcel_result_desc *rdesc;
@ -353,7 +353,7 @@
cdesc->control_data.control0 = CONTEXT_CONTROL_INV_TR;
/* Prepare result descriptor */
@@ -1003,7 +1048,7 @@
@@ -1003,7 +1048,7 @@ handle_results:
acknowledge:
if (i)
writel(EIP197_xDR_PROC_xD_PKT(i) |
@ -362,7 +362,7 @@
EIP197_HIA_RDR(priv, ring) + EIP197_HIA_xDR_PROC_COUNT);
/* If the number of requests overflowed the counter, try to proceed more
@@ -1171,6 +1216,44 @@
@@ -1171,6 +1216,44 @@ static struct safexcel_alg_template *saf
&safexcel_alg_xts_aes,
&safexcel_alg_gcm,
&safexcel_alg_ccm,
@ -407,7 +407,7 @@
};
static int safexcel_register_algorithms(struct safexcel_crypto_priv *priv)
@@ -1240,30 +1323,30 @@
@@ -1240,30 +1323,30 @@ static void safexcel_unregister_algorith
static void safexcel_configure(struct safexcel_crypto_priv *priv)
{
@ -457,7 +457,7 @@
}
static void safexcel_init_register_offsets(struct safexcel_crypto_priv *priv)
@@ -1309,7 +1392,7 @@
@@ -1309,7 +1392,7 @@ static int safexcel_probe_generic(void *
int is_pci_dev)
{
struct device *dev = priv->dev;
@ -466,7 +466,7 @@
int i, ret, hwctg;
priv->context_pool = dmam_pool_create("safexcel-context", dev,
@@ -1371,13 +1454,16 @@
@@ -1371,13 +1454,16 @@ static int safexcel_probe_generic(void *
*/
version = readl(EIP197_GLOBAL(priv) + EIP197_VERSION);
if (((priv->flags & SAFEXCEL_HW_EIP197) &&
@ -484,7 +484,7 @@
return -ENODEV;
}
@@ -1385,6 +1471,14 @@
@@ -1385,6 +1471,14 @@ static int safexcel_probe_generic(void *
hwctg = version >> 28;
peid = version & 255;
@ -499,7 +499,7 @@
/* Detect EIP96 packet engine and version */
version = readl(EIP197_PE(priv) + EIP197_PE_EIP96_VERSION(0));
if (EIP197_REG_LO16(version) != EIP96_VERSION_LE) {
@@ -1393,10 +1487,13 @@
@@ -1393,10 +1487,13 @@ static int safexcel_probe_generic(void *
}
priv->hwconfig.pever = EIP197_VERSION_MASK(version);
@ -513,7 +513,7 @@
priv->hwconfig.hwdataw = (hiaopt >> EIP197_HWDATAW_OFFSET) &
EIP197_HWDATAW_MASK;
priv->hwconfig.hwcfsize = ((hiaopt >> EIP197_CFSIZE_OFFSET) &
@@ -1405,6 +1502,19 @@
@@ -1405,6 +1502,19 @@ static int safexcel_probe_generic(void *
priv->hwconfig.hwrfsize = ((hiaopt >> EIP197_RFSIZE_OFFSET) &
EIP197_RFSIZE_MASK) +
EIP197_RFSIZE_ADJUST;
@ -533,7 +533,7 @@
} else {
/* EIP97 */
priv->hwconfig.hwdataw = (hiaopt >> EIP197_HWDATAW_OFFSET) &
@@ -1413,6 +1523,23 @@
@@ -1413,6 +1523,23 @@ static int safexcel_probe_generic(void *
EIP97_CFSIZE_MASK;
priv->hwconfig.hwrfsize = (hiaopt >> EIP97_RFSIZE_OFFSET) &
EIP97_RFSIZE_MASK;
@ -557,7 +557,7 @@
}
/* Get supported algorithms from EIP96 transform engine */
@@ -1420,10 +1547,12 @@
@@ -1420,10 +1547,12 @@ static int safexcel_probe_generic(void *
EIP197_PE_EIP96_OPTIONS(0));
/* Print single info line describing what we just detected */
@ -574,7 +574,7 @@
priv->hwconfig.algo_flags);
safexcel_configure(priv);
@@ -1547,7 +1676,6 @@
@@ -1547,7 +1676,6 @@ static void safexcel_hw_reset_rings(stru
}
}
@ -582,7 +582,7 @@
/* for Device Tree platform driver */
static int safexcel_probe(struct platform_device *pdev)
@@ -1625,6 +1753,7 @@
@@ -1625,6 +1753,7 @@ static int safexcel_remove(struct platfo
safexcel_unregister_algorithms(priv);
safexcel_hw_reset_rings(priv);
@ -590,7 +590,7 @@
clk_disable_unprepare(priv->clk);
for (i = 0; i < priv->config.rings; i++)
@@ -1666,9 +1795,7 @@
@@ -1666,9 +1795,7 @@ static struct platform_driver crypto_sa
.of_match_table = safexcel_of_match_table,
},
};
@ -600,7 +600,7 @@
/* PCIE devices - i.e. Inside Secure development boards */
static int safexcel_pci_probe(struct pci_dev *pdev,
@@ -1759,7 +1886,7 @@
@@ -1759,7 +1886,7 @@ static int safexcel_pci_probe(struct pci
return rc;
}
@ -609,7 +609,7 @@
{
struct safexcel_crypto_priv *priv = pci_get_drvdata(pdev);
int i;
@@ -1789,54 +1916,32 @@
@@ -1789,54 +1916,32 @@ static struct pci_driver safexcel_pci_dr
.probe = safexcel_pci_probe,
.remove = safexcel_pci_remove,
};
@ -702,7 +702,7 @@
#include <crypto/xts.h>
#include <crypto/skcipher.h>
#include <crypto/internal/aead.h>
@@ -33,6 +37,8 @@
@@ -33,6 +37,8 @@ enum safexcel_cipher_alg {
SAFEXCEL_DES,
SAFEXCEL_3DES,
SAFEXCEL_AES,
@ -711,7 +711,7 @@
};
struct safexcel_cipher_ctx {
@@ -41,8 +47,12 @@
@@ -41,8 +47,12 @@ struct safexcel_cipher_ctx {
u32 mode;
enum safexcel_cipher_alg alg;
@ -726,7 +726,7 @@
__le32 key[16];
u32 nonce;
@@ -51,10 +61,11 @@
@@ -51,10 +61,11 @@ struct safexcel_cipher_ctx {
/* All the below is AEAD specific */
u32 hash_alg;
u32 state_sz;
@ -740,7 +740,7 @@
};
struct safexcel_cipher_req {
@@ -65,206 +76,298 @@
@@ -65,206 +76,298 @@ struct safexcel_cipher_req {
int nr_src, nr_dst;
};
@ -1201,7 +1201,7 @@
}
static int safexcel_skcipher_aes_setkey(struct crypto_skcipher *ctfm,
@@ -277,14 +380,12 @@
@@ -277,14 +380,12 @@ static int safexcel_skcipher_aes_setkey(
int ret, i;
ret = aes_expandkey(&aes, key, len);
@ -1218,7 +1218,7 @@
ctx->base.needs_inv = true;
break;
}
@@ -309,43 +410,57 @@
@@ -309,43 +410,57 @@ static int safexcel_aead_setkey(struct c
struct safexcel_crypto_priv *priv = ctx->priv;
struct crypto_authenc_keys keys;
struct crypto_aes_ctx aes;
@ -1286,7 +1286,7 @@
/* Auth key */
switch (ctx->hash_alg) {
@@ -374,21 +489,24 @@
@@ -374,21 +489,24 @@ static int safexcel_aead_setkey(struct c
keys.authkeylen, &istate, &ostate))
goto badkey;
break;
@ -1315,7 +1315,7 @@
ctx->key_len = keys.enckeylen;
memcpy(ctx->ipad, &istate.state, ctx->state_sz);
@@ -398,8 +516,6 @@
@@ -398,8 +516,6 @@ static int safexcel_aead_setkey(struct c
return 0;
badkey:
@ -1324,7 +1324,7 @@
memzero_explicit(&keys, sizeof(keys));
return err;
}
@@ -423,6 +539,17 @@
@@ -423,6 +539,17 @@ static int safexcel_context_control(stru
CONTEXT_CONTROL_DIGEST_XCM |
ctx->hash_alg |
CONTEXT_CONTROL_SIZE(ctrl_size);
@ -1342,7 +1342,7 @@
} else {
ctrl_size += ctx->state_sz / sizeof(u32) * 2;
cdesc->control_data.control0 =
@@ -431,17 +558,21 @@
@@ -431,17 +558,21 @@ static int safexcel_context_control(stru
ctx->hash_alg |
CONTEXT_CONTROL_SIZE(ctrl_size);
}
@ -1372,7 +1372,7 @@
} else {
if (sreq->direction == SAFEXCEL_ENCRYPT)
cdesc->control_data.control0 =
@@ -480,6 +611,12 @@
@@ -480,6 +611,12 @@ static int safexcel_context_control(stru
ctx->key_len >> ctx->xts);
return -EINVAL;
}
@ -1385,7 +1385,7 @@
}
return 0;
@@ -563,6 +700,7 @@
@@ -563,6 +700,7 @@ static int safexcel_send_req(struct cryp
unsigned int totlen;
unsigned int totlen_src = cryptlen + assoclen;
unsigned int totlen_dst = totlen_src;
@ -1393,7 +1393,7 @@
int n_cdesc = 0, n_rdesc = 0;
int queued, i, ret = 0;
bool first = true;
@@ -637,56 +775,60 @@
@@ -637,56 +775,60 @@ static int safexcel_send_req(struct cryp
memcpy(ctx->base.ctxr->data, ctx->key, ctx->key_len);
@ -1475,7 +1475,7 @@
cryptlen);
/* result descriptors */
@@ -1073,6 +1215,8 @@
@@ -1073,6 +1215,8 @@ static int safexcel_skcipher_cra_init(st
ctx->base.send = safexcel_skcipher_send;
ctx->base.handle_result = safexcel_skcipher_handle_result;
@ -1484,7 +1484,7 @@
return 0;
}
@@ -1137,6 +1281,8 @@
@@ -1137,6 +1281,8 @@ static int safexcel_skcipher_aes_ecb_cra
safexcel_skcipher_cra_init(tfm);
ctx->alg = SAFEXCEL_AES;
ctx->mode = CONTEXT_CONTROL_CRYPTO_MODE_ECB;
@ -1493,7 +1493,7 @@
return 0;
}
@@ -1171,6 +1317,7 @@
@@ -1171,6 +1317,7 @@ static int safexcel_skcipher_aes_cbc_cra
safexcel_skcipher_cra_init(tfm);
ctx->alg = SAFEXCEL_AES;
@ -1501,7 +1501,7 @@
ctx->mode = CONTEXT_CONTROL_CRYPTO_MODE_CBC;
return 0;
}
@@ -1207,6 +1354,7 @@
@@ -1207,6 +1354,7 @@ static int safexcel_skcipher_aes_cfb_cra
safexcel_skcipher_cra_init(tfm);
ctx->alg = SAFEXCEL_AES;
@ -1509,7 +1509,7 @@
ctx->mode = CONTEXT_CONTROL_CRYPTO_MODE_CFB;
return 0;
}
@@ -1243,6 +1391,7 @@
@@ -1243,6 +1391,7 @@ static int safexcel_skcipher_aes_ofb_cra
safexcel_skcipher_cra_init(tfm);
ctx->alg = SAFEXCEL_AES;
@ -1517,7 +1517,7 @@
ctx->mode = CONTEXT_CONTROL_CRYPTO_MODE_OFB;
return 0;
}
@@ -1288,14 +1437,12 @@
@@ -1288,14 +1437,12 @@ static int safexcel_skcipher_aesctr_setk
/* exclude the nonce here */
keylen = len - CTR_RFC3686_NONCE_SIZE;
ret = aes_expandkey(&aes, key, keylen);
@ -1534,7 +1534,7 @@
ctx->base.needs_inv = true;
break;
}
@@ -1317,6 +1464,7 @@
@@ -1317,6 +1464,7 @@ static int safexcel_skcipher_aes_ctr_cra
safexcel_skcipher_cra_init(tfm);
ctx->alg = SAFEXCEL_AES;
@ -1542,7 +1542,7 @@
ctx->mode = CONTEXT_CONTROL_CRYPTO_MODE_CTR_LOAD;
return 0;
}
@@ -1352,6 +1500,7 @@
@@ -1352,6 +1500,7 @@ static int safexcel_des_setkey(struct cr
unsigned int len)
{
struct safexcel_cipher_ctx *ctx = crypto_skcipher_ctx(ctfm);
@ -1550,7 +1550,7 @@
int ret;
ret = verify_skcipher_des_key(ctfm, key);
@@ -1359,7 +1508,7 @@
@@ -1359,7 +1508,7 @@ static int safexcel_des_setkey(struct cr
return ret;
/* if context exits and key changed, need to invalidate it */
@ -1559,7 +1559,7 @@
if (memcmp(ctx->key, key, len))
ctx->base.needs_inv = true;
@@ -1375,6 +1524,8 @@
@@ -1375,6 +1524,8 @@ static int safexcel_skcipher_des_cbc_cra
safexcel_skcipher_cra_init(tfm);
ctx->alg = SAFEXCEL_DES;
@ -1568,7 +1568,7 @@
ctx->mode = CONTEXT_CONTROL_CRYPTO_MODE_CBC;
return 0;
}
@@ -1412,6 +1563,8 @@
@@ -1412,6 +1563,8 @@ static int safexcel_skcipher_des_ecb_cra
safexcel_skcipher_cra_init(tfm);
ctx->alg = SAFEXCEL_DES;
ctx->mode = CONTEXT_CONTROL_CRYPTO_MODE_ECB;
@ -1577,7 +1577,7 @@
return 0;
}
@@ -1444,6 +1597,7 @@
@@ -1444,6 +1597,7 @@ static int safexcel_des3_ede_setkey(stru
const u8 *key, unsigned int len)
{
struct safexcel_cipher_ctx *ctx = crypto_skcipher_ctx(ctfm);
@ -1585,7 +1585,7 @@
int err;
err = verify_skcipher_des3_key(ctfm, key);
@@ -1451,13 +1605,11 @@
@@ -1451,13 +1605,11 @@ static int safexcel_des3_ede_setkey(stru
return err;
/* if context exits and key changed, need to invalidate it */
@ -1600,7 +1600,7 @@
ctx->key_len = len;
return 0;
@@ -1469,6 +1621,8 @@
@@ -1469,6 +1621,8 @@ static int safexcel_skcipher_des3_cbc_cr
safexcel_skcipher_cra_init(tfm);
ctx->alg = SAFEXCEL_3DES;
@ -1609,7 +1609,7 @@
ctx->mode = CONTEXT_CONTROL_CRYPTO_MODE_CBC;
return 0;
}
@@ -1506,6 +1660,8 @@
@@ -1506,6 +1660,8 @@ static int safexcel_skcipher_des3_ecb_cr
safexcel_skcipher_cra_init(tfm);
ctx->alg = SAFEXCEL_3DES;
ctx->mode = CONTEXT_CONTROL_CRYPTO_MODE_ECB;
@ -1618,7 +1618,7 @@
return 0;
}
@@ -1561,6 +1717,9 @@
@@ -1561,6 +1717,9 @@ static int safexcel_aead_cra_init(struct
ctx->priv = tmpl->priv;
ctx->alg = SAFEXCEL_AES; /* default */
@ -1628,7 +1628,7 @@
ctx->mode = CONTEXT_CONTROL_CRYPTO_MODE_CBC; /* default */
ctx->aead = true;
ctx->base.send = safexcel_aead_send;
@@ -1749,6 +1908,8 @@
@@ -1749,6 +1908,8 @@ static int safexcel_aead_sha1_des3_cra_i
safexcel_aead_sha1_cra_init(tfm);
ctx->alg = SAFEXCEL_3DES; /* override default */
@ -1637,7 +1637,7 @@
return 0;
}
@@ -1777,6 +1938,330 @@
@@ -1777,6 +1938,330 @@ struct safexcel_alg_template safexcel_al
},
};
@ -1968,7 +1968,7 @@
static int safexcel_aead_sha1_ctr_cra_init(struct crypto_tfm *tfm)
{
struct safexcel_cipher_ctx *ctx = crypto_tfm_ctx(tfm);
@@ -1965,14 +2450,12 @@
@@ -1965,14 +2450,12 @@ static int safexcel_skcipher_aesxts_setk
/* Only half of the key data is cipher key */
keylen = (len >> 1);
ret = aes_expandkey(&aes, key, keylen);
@ -1985,7 +1985,7 @@
ctx->base.needs_inv = true;
break;
}
@@ -1984,15 +2467,13 @@
@@ -1984,15 +2467,13 @@ static int safexcel_skcipher_aesxts_setk
/* The other half is the tweak key */
ret = aes_expandkey(&aes, (u8 *)(key + keylen), keylen);
@ -2004,7 +2004,7 @@
ctx->base.needs_inv = true;
break;
}
@@ -2015,6 +2496,7 @@
@@ -2015,6 +2496,7 @@ static int safexcel_skcipher_aes_xts_cra
safexcel_skcipher_cra_init(tfm);
ctx->alg = SAFEXCEL_AES;
@ -2012,7 +2012,7 @@
ctx->xts = 1;
ctx->mode = CONTEXT_CONTROL_CRYPTO_MODE_XTS;
return 0;
@@ -2075,14 +2557,13 @@
@@ -2075,14 +2557,13 @@ static int safexcel_aead_gcm_setkey(stru
ret = aes_expandkey(&aes, key, len);
if (ret) {
@ -2028,7 +2028,7 @@
ctx->base.needs_inv = true;
break;
}
@@ -2099,8 +2580,6 @@
@@ -2099,8 +2580,6 @@ static int safexcel_aead_gcm_setkey(stru
crypto_cipher_set_flags(ctx->hkaes, crypto_aead_get_flags(ctfm) &
CRYPTO_TFM_REQ_MASK);
ret = crypto_cipher_setkey(ctx->hkaes, key, len);
@ -2037,7 +2037,7 @@
if (ret)
return ret;
@@ -2109,7 +2588,7 @@
@@ -2109,7 +2588,7 @@ static int safexcel_aead_gcm_setkey(stru
if (priv->flags & EIP197_TRC_CACHE && ctx->base.ctxr_dma) {
for (i = 0; i < AES_BLOCK_SIZE / sizeof(u32); i++) {
@ -2046,7 +2046,7 @@
ctx->base.needs_inv = true;
break;
}
@@ -2135,10 +2614,7 @@
@@ -2135,10 +2614,7 @@ static int safexcel_aead_gcm_cra_init(st
ctx->mode = CONTEXT_CONTROL_CRYPTO_MODE_XCM; /* override default */
ctx->hkaes = crypto_alloc_cipher("aes", 0, 0);
@ -2058,7 +2058,7 @@
}
static void safexcel_aead_gcm_cra_exit(struct crypto_tfm *tfm)
@@ -2192,14 +2668,13 @@
@@ -2192,14 +2668,13 @@ static int safexcel_aead_ccm_setkey(stru
ret = aes_expandkey(&aes, key, len);
if (ret) {
@ -2074,7 +2074,7 @@
ctx->base.needs_inv = true;
break;
}
@@ -2235,6 +2710,7 @@
@@ -2235,6 +2710,7 @@ static int safexcel_aead_ccm_cra_init(st
ctx->state_sz = 3 * AES_BLOCK_SIZE;
ctx->xcm = EIP197_XCM_MODE_CCM;
ctx->mode = CONTEXT_CONTROL_CRYPTO_MODE_XCM; /* override default */
@ -2082,7 +2082,7 @@
return 0;
}
@@ -2301,5 +2777,949 @@
@@ -2301,5 +2777,949 @@ struct safexcel_alg_template safexcel_al
.cra_exit = safexcel_aead_cra_exit,
.cra_module = THIS_MODULE,
},
@ -3183,7 +3183,7 @@
__le32 data[40];
} __packed;
@@ -358,10 +388,14 @@
@@ -358,10 +388,14 @@ struct safexcel_context_record {
#define CONTEXT_CONTROL_CRYPTO_ALG_AES128 (0x5 << 17)
#define CONTEXT_CONTROL_CRYPTO_ALG_AES192 (0x6 << 17)
#define CONTEXT_CONTROL_CRYPTO_ALG_AES256 (0x7 << 17)
@ -3198,7 +3198,7 @@
#define CONTEXT_CONTROL_CRYPTO_ALG_SHA1 (0x2 << 23)
#define CONTEXT_CONTROL_CRYPTO_ALG_SHA224 (0x4 << 23)
#define CONTEXT_CONTROL_CRYPTO_ALG_SHA256 (0x3 << 23)
@@ -371,17 +405,25 @@
@@ -371,17 +405,25 @@ struct safexcel_context_record {
#define CONTEXT_CONTROL_CRYPTO_ALG_XCBC128 (0x1 << 23)
#define CONTEXT_CONTROL_CRYPTO_ALG_XCBC192 (0x2 << 23)
#define CONTEXT_CONTROL_CRYPTO_ALG_XCBC256 (0x3 << 23)
@ -3224,7 +3224,7 @@
#define CONTEXT_CONTROL_IV0 BIT(5)
#define CONTEXT_CONTROL_IV1 BIT(6)
#define CONTEXT_CONTROL_IV2 BIT(7)
@@ -394,6 +436,13 @@
@@ -394,6 +436,13 @@ struct safexcel_context_record {
#define EIP197_XCM_MODE_GCM 1
#define EIP197_XCM_MODE_CCM 2
@ -3238,7 +3238,7 @@
/* The hash counter given to the engine in the context has a granularity of
* 64 bits.
*/
@@ -423,6 +472,8 @@
@@ -423,6 +472,8 @@ struct safexcel_context_record {
#define EIP197_TRC_PARAMS2_RC_SZ_SMALL(n) ((n) << 18)
/* Cache helpers */
@ -3247,7 +3247,7 @@
#define EIP197_CS_TRC_REC_WC 64
#define EIP197_CS_RC_SIZE (4 * sizeof(u32))
#define EIP197_CS_RC_NEXT(x) (x)
@@ -447,7 +498,7 @@
@@ -447,7 +498,7 @@ struct result_data_desc {
u16 application_id;
u16 rsvd1;
@ -3256,7 +3256,7 @@
} __packed;
@@ -465,16 +516,15 @@
@@ -465,16 +516,15 @@ struct safexcel_result_desc {
u32 data_lo;
u32 data_hi;
@ -3276,7 +3276,7 @@
sizeof(u32))
struct safexcel_token {
@@ -505,6 +555,8 @@
@@ -505,6 +555,8 @@ static inline void eip197_noop_token(str
{
token->opcode = EIP197_TOKEN_OPCODE_NOOP;
token->packet_length = BIT(2);
@ -3285,7 +3285,7 @@
}
/* Instructions */
@@ -526,14 +578,13 @@
@@ -526,14 +578,13 @@ struct safexcel_control_data_desc {
u16 application_id;
u16 rsvd;
@ -3302,7 +3302,7 @@
} __packed;
#define EIP197_OPTION_MAGIC_VALUE BIT(0)
@@ -543,7 +594,10 @@
@@ -543,7 +594,10 @@ struct safexcel_control_data_desc {
#define EIP197_OPTION_2_TOKEN_IV_CMD GENMASK(11, 10)
#define EIP197_OPTION_4_TOKEN_IV_CMD GENMASK(11, 9)
@ -3313,7 +3313,7 @@
/* Basic Command Descriptor format */
struct safexcel_command_desc {
@@ -551,16 +605,22 @@
@@ -551,16 +605,22 @@ struct safexcel_command_desc {
u8 rsvd0:5;
u8 last_seg:1;
u8 first_seg:1;
@ -3337,7 +3337,7 @@
/*
* Internal structures & functions
*/
@@ -578,15 +638,20 @@
@@ -578,15 +638,20 @@ enum eip197_fw {
struct safexcel_desc_ring {
void *base;
@ -3359,7 +3359,7 @@
};
enum safexcel_alg_type {
@@ -601,9 +666,11 @@
@@ -601,9 +666,11 @@ struct safexcel_config {
u32 cd_size;
u32 cd_offset;
@ -3371,7 +3371,7 @@
};
struct safexcel_work_data {
@@ -654,6 +721,12 @@
@@ -654,6 +721,12 @@ enum safexcel_eip_version {
/* Priority we use for advertising our algorithms */
#define SAFEXCEL_CRA_PRIORITY 300
@ -3384,7 +3384,7 @@
/* EIP algorithm presence flags */
enum safexcel_eip_algorithms {
SAFEXCEL_ALG_BC0 = BIT(5),
@@ -697,16 +770,23 @@
@@ -697,16 +770,23 @@ struct safexcel_register_offsets {
enum safexcel_flags {
EIP197_TRC_CACHE = BIT(0),
SAFEXCEL_HW_EIP197 = BIT(1),
@ -3408,7 +3408,7 @@
};
struct safexcel_crypto_priv {
@@ -778,7 +858,7 @@
@@ -778,7 +858,7 @@ struct safexcel_inv_result {
void safexcel_dequeue(struct safexcel_crypto_priv *priv, int ring);
int safexcel_rdesc_check_errors(struct safexcel_crypto_priv *priv,
@ -3417,7 +3417,7 @@
void safexcel_complete(struct safexcel_crypto_priv *priv, int ring);
int safexcel_invalidate_cache(struct crypto_async_request *async,
struct safexcel_crypto_priv *priv,
@@ -797,7 +877,8 @@
@@ -797,7 +877,8 @@ struct safexcel_command_desc *safexcel_a
bool first, bool last,
dma_addr_t data, u32 len,
u32 full_data_len,
@ -3427,7 +3427,7 @@
struct safexcel_result_desc *safexcel_add_rdesc(struct safexcel_crypto_priv *priv,
int ring_id,
bool first, bool last,
@@ -853,5 +934,43 @@
@@ -853,5 +934,43 @@ extern struct safexcel_alg_template safe
extern struct safexcel_alg_template safexcel_alg_xts_aes;
extern struct safexcel_alg_template safexcel_alg_gcm;
extern struct safexcel_alg_template safexcel_alg_ccm;
@ -3487,7 +3487,7 @@
#include <linux/device.h>
#include <linux/dma-mapping.h>
#include <linux/dmapool.h>
@@ -19,9 +23,19 @@
@@ -19,9 +23,19 @@ struct safexcel_ahash_ctx {
struct safexcel_crypto_priv *priv;
u32 alg;
@ -3510,7 +3510,7 @@
};
struct safexcel_ahash_req {
@@ -31,6 +45,8 @@
@@ -31,6 +45,8 @@ struct safexcel_ahash_req {
bool needs_inv;
bool hmac_zlen;
bool len_is_le;
@ -3519,7 +3519,7 @@
int nents;
dma_addr_t result_dma;
@@ -39,7 +55,9 @@
@@ -39,7 +55,9 @@ struct safexcel_ahash_req {
u8 state_sz; /* expected state size, only set once */
u8 block_sz; /* block size, only set once */
@ -3530,7 +3530,7 @@
u64 len;
u64 processed;
@@ -57,22 +75,36 @@
@@ -57,22 +75,36 @@ static inline u64 safexcel_queued_len(st
}
static void safexcel_hash_token(struct safexcel_command_desc *cdesc,
@ -3573,7 +3573,7 @@
}
static void safexcel_context_control(struct safexcel_ahash_ctx *ctx,
@@ -82,29 +114,49 @@
@@ -82,29 +114,49 @@ static void safexcel_context_control(str
struct safexcel_crypto_priv *priv = ctx->priv;
u64 count = 0;
@ -3630,7 +3630,7 @@
return;
}
@@ -204,7 +256,7 @@
@@ -204,7 +256,7 @@ static int safexcel_handle_req_result(st
}
if (sreq->result_dma) {
@ -3639,7 +3639,7 @@
DMA_FROM_DEVICE);
sreq->result_dma = 0;
}
@@ -223,14 +275,15 @@
@@ -223,14 +275,15 @@ static int safexcel_handle_req_result(st
memcpy(sreq->cache, sreq->state,
crypto_ahash_digestsize(ahash));
@ -3657,7 +3657,7 @@
areq->nbytes = 0;
safexcel_ahash_enqueue(areq);
@@ -238,8 +291,14 @@
@@ -238,8 +291,14 @@ static int safexcel_handle_req_result(st
return 1;
}
@ -3674,7 +3674,7 @@
}
cache_len = safexcel_queued_len(sreq);
@@ -261,10 +320,11 @@
@@ -261,10 +320,11 @@ static int safexcel_ahash_send_req(struc
struct safexcel_command_desc *cdesc, *first_cdesc = NULL;
struct safexcel_result_desc *rdesc;
struct scatterlist *sg;
@ -3689,7 +3689,7 @@
if (queued <= HASH_CACHE_SIZE)
cache_len = queued;
else
@@ -287,15 +347,52 @@
@@ -287,15 +347,52 @@ static int safexcel_ahash_send_req(struc
areq->nbytes - extra);
queued -= extra;
@ -3743,7 +3743,7 @@
/* Add a command descriptor for the cached data, if any */
if (cache_len) {
req->cache_dma = dma_map_single(priv->dev, req->cache,
@@ -306,8 +403,9 @@
@@ -306,8 +403,9 @@ static int safexcel_ahash_send_req(struc
req->cache_sz = cache_len;
first_cdesc = safexcel_add_cdesc(priv, ring, 1,
(cache_len == len),
@ -3755,7 +3755,7 @@
if (IS_ERR(first_cdesc)) {
ret = PTR_ERR(first_cdesc);
goto unmap_cache;
@@ -319,10 +417,6 @@
@@ -319,10 +417,6 @@ static int safexcel_ahash_send_req(struc
goto send_command;
}
@ -3766,7 +3766,7 @@
/* Now handle the current ahash request buffer(s) */
req->nents = dma_map_sg(priv->dev, areq->src,
sg_nents_for_len(areq->src,
@@ -336,26 +430,34 @@
@@ -336,26 +430,34 @@ static int safexcel_ahash_send_req(struc
for_each_sg(areq->src, sg, req->nents, i) {
int sglen = sg_dma_len(sg);
@ -3806,7 +3806,7 @@
}
send_command:
@@ -363,9 +465,9 @@
@@ -363,9 +465,9 @@ send_command:
safexcel_context_control(ctx, req, first_cdesc);
/* Add the token */
@ -3818,7 +3818,7 @@
DMA_FROM_DEVICE);
if (dma_mapping_error(priv->dev, req->result_dma)) {
ret = -EINVAL;
@@ -374,7 +476,7 @@
@@ -374,7 +476,7 @@ send_command:
/* Add a result descriptor */
rdesc = safexcel_add_rdesc(priv, ring, 1, 1, req->result_dma,
@ -3827,7 +3827,7 @@
if (IS_ERR(rdesc)) {
ret = PTR_ERR(rdesc);
goto unmap_result;
@@ -382,17 +484,20 @@
@@ -382,17 +484,20 @@ send_command:
safexcel_rdr_req_set(priv, ring, rdesc, &areq->base);
@ -3851,7 +3851,7 @@
cdesc_rollback:
for (i = 0; i < n_cdesc; i++)
safexcel_ring_rollback_wptr(priv, &priv->ring[ring].cdr);
@@ -590,16 +695,12 @@
@@ -590,16 +695,12 @@ static int safexcel_ahash_enqueue(struct
if (ctx->base.ctxr) {
if (priv->flags & EIP197_TRC_CACHE && !ctx->base.needs_inv &&
@ -3871,7 +3871,7 @@
memcmp(ctx->base.ctxr->data + (req->state_sz>>2),
ctx->opad, req->state_sz))))
/*
@@ -622,6 +723,7 @@
@@ -622,6 +723,7 @@ static int safexcel_ahash_enqueue(struct
if (!ctx->base.ctxr)
return -ENOMEM;
}
@ -3879,7 +3879,7 @@
ring = ctx->base.ring;
@@ -691,8 +793,34 @@
@@ -691,8 +793,34 @@ static int safexcel_ahash_final(struct a
else if (ctx->alg == CONTEXT_CONTROL_CRYPTO_ALG_SHA512)
memcpy(areq->result, sha512_zero_message_hash,
SHA512_DIGEST_SIZE);
@ -3914,7 +3914,7 @@
} else if (unlikely(req->hmac &&
(req->len == req->block_sz) &&
!areq->nbytes)) {
@@ -792,6 +920,7 @@
@@ -792,6 +920,7 @@ static int safexcel_ahash_cra_init(struc
ctx->priv = tmpl->priv;
ctx->base.send = safexcel_ahash_send;
ctx->base.handle_result = safexcel_handle_result;
@ -3922,7 +3922,7 @@
crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
sizeof(struct safexcel_ahash_req));
@@ -808,6 +937,7 @@
@@ -808,6 +937,7 @@ static int safexcel_sha1_init(struct aha
ctx->alg = CONTEXT_CONTROL_CRYPTO_ALG_SHA1;
req->digest = CONTEXT_CONTROL_DIGEST_PRECOMPUTED;
req->state_sz = SHA1_DIGEST_SIZE;
@ -3930,7 +3930,7 @@
req->block_sz = SHA1_BLOCK_SIZE;
return 0;
@@ -889,6 +1019,7 @@
@@ -889,6 +1019,7 @@ static int safexcel_hmac_sha1_init(struc
ctx->alg = CONTEXT_CONTROL_CRYPTO_ALG_SHA1;
req->digest = CONTEXT_CONTROL_DIGEST_PRECOMPUTED;
req->state_sz = SHA1_DIGEST_SIZE;
@ -3938,7 +3938,7 @@
req->block_sz = SHA1_BLOCK_SIZE;
req->hmac = true;
@@ -1125,6 +1256,7 @@
@@ -1125,6 +1256,7 @@ static int safexcel_sha256_init(struct a
ctx->alg = CONTEXT_CONTROL_CRYPTO_ALG_SHA256;
req->digest = CONTEXT_CONTROL_DIGEST_PRECOMPUTED;
req->state_sz = SHA256_DIGEST_SIZE;
@ -3946,7 +3946,7 @@
req->block_sz = SHA256_BLOCK_SIZE;
return 0;
@@ -1180,6 +1312,7 @@
@@ -1180,6 +1312,7 @@ static int safexcel_sha224_init(struct a
ctx->alg = CONTEXT_CONTROL_CRYPTO_ALG_SHA224;
req->digest = CONTEXT_CONTROL_DIGEST_PRECOMPUTED;
req->state_sz = SHA256_DIGEST_SIZE;
@ -3954,7 +3954,7 @@
req->block_sz = SHA256_BLOCK_SIZE;
return 0;
@@ -1248,6 +1381,7 @@
@@ -1248,6 +1381,7 @@ static int safexcel_hmac_sha224_init(str
ctx->alg = CONTEXT_CONTROL_CRYPTO_ALG_SHA224;
req->digest = CONTEXT_CONTROL_DIGEST_PRECOMPUTED;
req->state_sz = SHA256_DIGEST_SIZE;
@ -3962,7 +3962,7 @@
req->block_sz = SHA256_BLOCK_SIZE;
req->hmac = true;
@@ -1318,6 +1452,7 @@
@@ -1318,6 +1452,7 @@ static int safexcel_hmac_sha256_init(str
ctx->alg = CONTEXT_CONTROL_CRYPTO_ALG_SHA256;
req->digest = CONTEXT_CONTROL_DIGEST_PRECOMPUTED;
req->state_sz = SHA256_DIGEST_SIZE;
@ -3970,7 +3970,7 @@
req->block_sz = SHA256_BLOCK_SIZE;
req->hmac = true;
@@ -1375,6 +1510,7 @@
@@ -1375,6 +1510,7 @@ static int safexcel_sha512_init(struct a
ctx->alg = CONTEXT_CONTROL_CRYPTO_ALG_SHA512;
req->digest = CONTEXT_CONTROL_DIGEST_PRECOMPUTED;
req->state_sz = SHA512_DIGEST_SIZE;
@ -3978,7 +3978,7 @@
req->block_sz = SHA512_BLOCK_SIZE;
return 0;
@@ -1430,6 +1566,7 @@
@@ -1430,6 +1566,7 @@ static int safexcel_sha384_init(struct a
ctx->alg = CONTEXT_CONTROL_CRYPTO_ALG_SHA384;
req->digest = CONTEXT_CONTROL_DIGEST_PRECOMPUTED;
req->state_sz = SHA512_DIGEST_SIZE;
@ -3986,7 +3986,7 @@
req->block_sz = SHA512_BLOCK_SIZE;
return 0;
@@ -1498,6 +1635,7 @@
@@ -1498,6 +1635,7 @@ static int safexcel_hmac_sha512_init(str
ctx->alg = CONTEXT_CONTROL_CRYPTO_ALG_SHA512;
req->digest = CONTEXT_CONTROL_DIGEST_PRECOMPUTED;
req->state_sz = SHA512_DIGEST_SIZE;
@ -3994,7 +3994,7 @@
req->block_sz = SHA512_BLOCK_SIZE;
req->hmac = true;
@@ -1568,6 +1706,7 @@
@@ -1568,6 +1706,7 @@ static int safexcel_hmac_sha384_init(str
ctx->alg = CONTEXT_CONTROL_CRYPTO_ALG_SHA384;
req->digest = CONTEXT_CONTROL_DIGEST_PRECOMPUTED;
req->state_sz = SHA512_DIGEST_SIZE;
@ -4002,7 +4002,7 @@
req->block_sz = SHA512_BLOCK_SIZE;
req->hmac = true;
@@ -1625,6 +1764,7 @@
@@ -1625,6 +1764,7 @@ static int safexcel_md5_init(struct ahas
ctx->alg = CONTEXT_CONTROL_CRYPTO_ALG_MD5;
req->digest = CONTEXT_CONTROL_DIGEST_PRECOMPUTED;
req->state_sz = MD5_DIGEST_SIZE;
@ -4010,7 +4010,7 @@
req->block_sz = MD5_HMAC_BLOCK_SIZE;
return 0;
@@ -1686,6 +1826,7 @@
@@ -1686,6 +1826,7 @@ static int safexcel_hmac_md5_init(struct
ctx->alg = CONTEXT_CONTROL_CRYPTO_ALG_MD5;
req->digest = CONTEXT_CONTROL_DIGEST_PRECOMPUTED;
req->state_sz = MD5_DIGEST_SIZE;
@ -4018,7 +4018,7 @@
req->block_sz = MD5_HMAC_BLOCK_SIZE;
req->len_is_le = true; /* MD5 is little endian! ... */
req->hmac = true;
@@ -1738,5 +1879,1235 @@
@@ -1738,5 +1879,1235 @@ struct safexcel_alg_template safexcel_al
.cra_module = THIS_MODULE,
},
},
@ -5256,7 +5256,7 @@
};
--- a/drivers/crypto/inside-secure/safexcel_ring.c
+++ b/drivers/crypto/inside-secure/safexcel_ring.c
@@ -14,7 +14,12 @@
@@ -14,7 +14,12 @@ int safexcel_init_ring_descriptors(struc
struct safexcel_desc_ring *cdr,
struct safexcel_desc_ring *rdr)
{
@ -5270,7 +5270,7 @@
cdr->base = dmam_alloc_coherent(priv->dev,
cdr->offset * EIP197_DEFAULT_RING_SIZE,
&cdr->base_dma, GFP_KERNEL);
@@ -24,7 +29,34 @@
@@ -24,7 +29,34 @@ int safexcel_init_ring_descriptors(struc
cdr->base_end = cdr->base + cdr->offset * (EIP197_DEFAULT_RING_SIZE - 1);
cdr->read = cdr->base;
@ -5306,7 +5306,7 @@
rdr->base = dmam_alloc_coherent(priv->dev,
rdr->offset * EIP197_DEFAULT_RING_SIZE,
&rdr->base_dma, GFP_KERNEL);
@@ -42,11 +74,40 @@
@@ -42,11 +74,40 @@ inline int safexcel_select_ring(struct s
return (atomic_inc_return(&priv->ring_used) % priv->config.rings);
}
@ -5349,7 +5349,7 @@
if ((ring->write == ring->read - ring->offset) ||
(ring->read == ring->base && ring->write == ring->base_end))
return ERR_PTR(-ENOMEM);
@@ -106,10 +167,13 @@
@@ -106,10 +167,13 @@ void safexcel_ring_rollback_wptr(struct
if (ring->write == ring->read)
return;
@ -5365,7 +5365,7 @@
}
struct safexcel_command_desc *safexcel_add_cdesc(struct safexcel_crypto_priv *priv,
@@ -117,26 +181,26 @@
@@ -117,26 +181,26 @@ struct safexcel_command_desc *safexcel_a
bool first, bool last,
dma_addr_t data, u32 data_len,
u32 full_data_len,
@ -5403,7 +5403,7 @@
/*
* Note that the length here MUST be >0 or else the EIP(1)97
* may hang. Newer EIP197 firmware actually incorporates this
@@ -146,20 +210,12 @@
@@ -146,20 +210,12 @@ struct safexcel_command_desc *safexcel_a
cdesc->control_data.packet_length = full_data_len ?: 1;
cdesc->control_data.options = EIP197_OPTION_MAGIC_VALUE |
EIP197_OPTION_64BIT_CTX |
@ -5429,7 +5429,7 @@
}
return cdesc;
@@ -171,18 +227,27 @@
@@ -171,18 +227,27 @@ struct safexcel_result_desc *safexcel_ad
dma_addr_t data, u32 len)
{
struct safexcel_result_desc *rdesc;

2
target/linux/mediatek/patches-5.4/0501-crypto-add-eip97-inside-secure-support.patch
View File

@ -1,6 +1,6 @@
--- a/drivers/crypto/inside-secure/safexcel.c
+++ b/drivers/crypto/inside-secure/safexcel.c
@@ -595,6 +595,14 @@
@@ -595,6 +595,14 @@ static int safexcel_hw_init(struct safex
val |= EIP197_MST_CTRL_TX_MAX_CMD(5);
writel(val, EIP197_HIA_AIC(priv) + EIP197_HIA_MST_CTRL);
}

38
target/linux/mediatek/patches-5.4/0600-1-6-net-dsa-mt7530-Refine-message-in-Kconfig.patch
View File

@ -78,23 +78,21 @@ Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
drivers/net/dsa/Kconfig | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/net/dsa/Kconfig b/drivers/net/dsa/Kconfig
index c7667645f04a..467f80157acf 100644
--- a/drivers/net/dsa/Kconfig
+++ b/drivers/net/dsa/Kconfig
@@ -33,12 +33,12 @@ config NET_DSA_LANTIQ_GSWIP
the xrx200 / VR9 SoC.
config NET_DSA_MT7530
- tristate "Mediatek MT7530 Ethernet switch support"
+ tristate "MediaTek MT7530 and MT7621 Ethernet switch support"
depends on NET_DSA
select NET_DSA_TAG_MTK
---help---
- This enables support for the Mediatek MT7530 Ethernet switch
- chip.
+ This enables support for the MediaTek MT7530 and MT7621 Ethernet
+ switch chip.
config NET_DSA_MV88E6060
tristate "Marvell 88E6060 ethernet switch chip support"
--- a/drivers/net/dsa/Kconfig
+++ b/drivers/net/dsa/Kconfig
@@ -33,12 +33,12 @@ config NET_DSA_LANTIQ_GSWIP
the xrx200 / VR9 SoC.
config NET_DSA_MT7530
- tristate "Mediatek MT7530 Ethernet switch support"
+ tristate "MediaTek MT7530 and MT7621 Ethernet switch support"
depends on NET_DSA
select NET_DSA_TAG_MTK
---help---
- This enables support for the Mediatek MT7530 Ethernet switch
- chip.
+ This enables support for the MediaTek MT7530 and MT7621 Ethernet
+ switch chip.
config NET_DSA_MV88E6060
tristate "Marvell 88E6060 ethernet switch chip support"

12
target/linux/mediatek/patches-5.4/0600-2-6-net-dsa-mt7530-Extend-device-data-ready-for-adding-a-new-hardware.patch
View File

@ -84,10 +84,8 @@ Signed-off-by: Sean Wang <sean.wang@mediatek.com>
drivers/net/dsa/mt7530.h | 29 ++++-
2 files changed, 203 insertions(+), 57 deletions(-)
Index: linux-5.4.43/drivers/net/dsa/mt7530.c
===================================================================
--- linux-5.4.43.orig/drivers/net/dsa/mt7530.c
+++ linux-5.4.43/drivers/net/dsa/mt7530.c
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
@@ -373,7 +373,7 @@ mt7530_fdb_write(struct mt7530_priv *pri
}
@ -389,10 +387,8 @@ Index: linux-5.4.43/drivers/net/dsa/mt7530.c
if (priv->id == ID_MT7530) {
priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core");
Index: linux-5.4.43/drivers/net/dsa/mt7530.h
===================================================================
--- linux-5.4.43.orig/drivers/net/dsa/mt7530.h
+++ linux-5.4.43/drivers/net/dsa/mt7530.h
--- a/drivers/net/dsa/mt7530.h
+++ b/drivers/net/dsa/mt7530.h
@@ -11,7 +11,7 @@
#define MT7530_NUM_FDB_RECORDS 2048
#define MT7530_ALL_MEMBERS 0xff

198
target/linux/mediatek/patches-5.4/0600-3-6-dt-bindings-net-dsa-add-new-MT7531-binding-to-support-MT7531.patch
View File

@ -79,103 +79,101 @@ Signed-off-by: Landen Chao <landen.chao@mediatek.com>
.../devicetree/bindings/net/dsa/mt7530.txt | 77 ++++++++++++++++++-
1 file changed, 74 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/dsa/mt7530.txt b/Documentation/devicetree/bindings/net/dsa/mt7530.txt
index c5ed5d25f642..dc226a4e402a 100644
--- a/Documentation/devicetree/bindings/net/dsa/mt7530.txt
+++ b/Documentation/devicetree/bindings/net/dsa/mt7530.txt
@@ -5,6 +5,7 @@ Required properties:
- compatible: may be compatible = "mediatek,mt7530"
or compatible = "mediatek,mt7621"
+ or compatible = "mediatek,mt7531"
- #address-cells: Must be 1.
- #size-cells: Must be 0.
- mediatek,mcm: Boolean; if defined, indicates that either MT7530 is the part
@@ -32,10 +33,13 @@ Required properties for the child nodes within ports container:
- reg: Port address described must be 6 for CPU port and from 0 to 5 for
user ports.
-- phy-mode: String, must be either "trgmii" or "rgmii" for port labeled
- "cpu".
+- phy-mode: String, the follow value would be acceptable for port labeled "cpu"
+ If compatible mediatek,mt7530 or mediatek,mt7621 is set,
+ must be either "trgmii" or "rgmii"
+ If compatible mediatek,mt7531 is set,
+ must be either "sgmii", "1000base-x" or "2500base-x"
-Port 5 of the switch is muxed between:
+Port 5 of mt7530 and mt7621 switch is muxed between:
1. GMAC5: GMAC5 can interface with another external MAC or PHY.
2. PHY of port 0 or port 4: PHY interfaces with an external MAC like 2nd GMAC
of the SOC. Used in many setups where port 0/4 becomes the WAN port.
@@ -308,3 +312,70 @@ Example 3: MT7621: Port 5 is connected to external PHY: Port 5 -> external PHY.
};
};
};
+
+Example 4:
+
+&eth {
+ gmac0: mac@0 {
+ compatible = "mediatek,eth-mac";
+ reg = <0>;
+ phy-mode = "2500base-x";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ pause;
+ };
+ };
+
+ &mdio0 {
+ switch@0 {
+ compatible = "mediatek,mt7531";
+ reg = <0>;
+ reset-gpios = <&pio 54 0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ port@0 {
+ reg = <0>;
+ label = "lan0";
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan1";
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan2";
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan3";
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "wan";
+ };
+
+ port@6 {
+ reg = <6>;
+ label = "cpu";
+ ethernet = <&gmac0>;
+ phy-mode = "2500base-x";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ pause;
+ };
+ };
+ };
+ };
+ };
--- a/Documentation/devicetree/bindings/net/dsa/mt7530.txt
+++ b/Documentation/devicetree/bindings/net/dsa/mt7530.txt
@@ -5,6 +5,7 @@ Required properties:
- compatible: may be compatible = "mediatek,mt7530"
or compatible = "mediatek,mt7621"
+ or compatible = "mediatek,mt7531"
- #address-cells: Must be 1.
- #size-cells: Must be 0.
- mediatek,mcm: Boolean; if defined, indicates that either MT7530 is the part
@@ -32,10 +33,13 @@ Required properties for the child nodes
- reg: Port address described must be 6 for CPU port and from 0 to 5 for
user ports.
-- phy-mode: String, must be either "trgmii" or "rgmii" for port labeled
- "cpu".
+- phy-mode: String, the follow value would be acceptable for port labeled "cpu"
+ If compatible mediatek,mt7530 or mediatek,mt7621 is set,
+ must be either "trgmii" or "rgmii"
+ If compatible mediatek,mt7531 is set,
+ must be either "sgmii", "1000base-x" or "2500base-x"
-Port 5 of the switch is muxed between:
+Port 5 of mt7530 and mt7621 switch is muxed between:
1. GMAC5: GMAC5 can interface with another external MAC or PHY.
2. PHY of port 0 or port 4: PHY interfaces with an external MAC like 2nd GMAC
of the SOC. Used in many setups where port 0/4 becomes the WAN port.
@@ -308,3 +312,70 @@ Example 3: MT7621: Port 5 is connected t
};
};
};
+
+Example 4:
+
+&eth {
+ gmac0: mac@0 {
+ compatible = "mediatek,eth-mac";
+ reg = <0>;
+ phy-mode = "2500base-x";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ pause;
+ };
+ };
+
+ &mdio0 {
+ switch@0 {
+ compatible = "mediatek,mt7531";
+ reg = <0>;
+ reset-gpios = <&pio 54 0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ port@0 {
+ reg = <0>;
+ label = "lan0";
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan1";
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan2";
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan3";
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "wan";
+ };
+
+ port@6 {
+ reg = <6>;
+ label = "cpu";
+ ethernet = <&gmac0>;
+ phy-mode = "2500base-x";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ pause;
+ };
+ };
+ };
+ };
+ };

18
target/linux/mediatek/patches-5.4/0600-4-6-net-dsa-mt7530-Add-the-support-of-MT7531-switch.patch
View File

@ -87,10 +87,8 @@ Signed-off-by: Sean Wang <sean.wang@mediatek.com>
drivers/net/dsa/mt7530.h | 144 +++++++++
3 files changed, 784 insertions(+), 9 deletions(-)
Index: linux-5.4.43/drivers/net/dsa/Kconfig
===================================================================
--- linux-5.4.43.orig/drivers/net/dsa/Kconfig
+++ linux-5.4.43/drivers/net/dsa/Kconfig
--- a/drivers/net/dsa/Kconfig
+++ b/drivers/net/dsa/Kconfig
@@ -33,12 +33,12 @@ config NET_DSA_LANTIQ_GSWIP
the xrx200 / VR9 SoC.
@ -107,10 +105,8 @@ Index: linux-5.4.43/drivers/net/dsa/Kconfig
config NET_DSA_MV88E6060
tristate "Marvell 88E6060 ethernet switch chip support"
Index: linux-5.4.43/drivers/net/dsa/mt7530.c
===================================================================
--- linux-5.4.43.orig/drivers/net/dsa/mt7530.c
+++ linux-5.4.43/drivers/net/dsa/mt7530.c
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
@@ -234,6 +234,12 @@ mt7530_write(struct mt7530_priv *priv, u
}
@ -882,10 +878,8 @@ Index: linux-5.4.43/drivers/net/dsa/mt7530.c
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, mt7530_of_match);
Index: linux-5.4.43/drivers/net/dsa/mt7530.h
===================================================================
--- linux-5.4.43.orig/drivers/net/dsa/mt7530.h
+++ linux-5.4.43/drivers/net/dsa/mt7530.h
--- a/drivers/net/dsa/mt7530.h
+++ b/drivers/net/dsa/mt7530.h
@@ -14,6 +14,7 @@
enum mt753x_id {
ID_MT7530 = 0,

120
target/linux/mediatek/patches-5.4/0600-6-6-arm64-dts-mt7622-add-mt7531-dsa-to-bananapi-bpi-r64-board.patch
View File

@ -77,64 +77,62 @@ Signed-off-by: Landen Chao <landen.chao@mediatek.com>
.../dts/mediatek/mt7622-bananapi-bpi-r64.dts | 50 +++++++++++++++++++
1 file changed, 50 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
index 83e10591e0e5..ffacefee8e2a 100644
--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
@@ -143,6 +143,56 @@
mdio: mdio-bus {
#address-cells = <1>;
#size-cells = <0>;
+
+ switch@0 {
+ compatible = "mediatek,mt7531";
+ reg = <0>;
+ reset-gpios = <&pio 54 0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ label = "wan";
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan0";
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan1";
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan2";
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "lan3";
+ };
+
+ port@6 {
+ reg = <6>;
+ label = "cpu";
+ ethernet = <&gmac0>;
+ phy-mode = "2500base-x";
+
+ fixed-link {
+ speed = <2500>;
+ full-duplex;
+ pause;
+ };
+ };
+ };
+ };
+
};
};
--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
@@ -150,6 +150,56 @@
mdio: mdio-bus {
#address-cells = <1>;
#size-cells = <0>;
+
+ switch@0 {
+ compatible = "mediatek,mt7531";
+ reg = <0>;
+ reset-gpios = <&pio 54 0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ label = "wan";
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan0";
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan1";
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan2";
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "lan3";
+ };
+
+ port@6 {
+ reg = <6>;
+ label = "cpu";
+ ethernet = <&gmac0>;
+ phy-mode = "2500base-x";
+
+ fixed-link {
+ speed = <2500>;
+ full-duplex;
+ pause;
+ };
+ };
+ };
+ };
+
};
};

7
target/linux/octeontx/patches-5.4/0002-gpio-thunderx-fix-irq_request_resources.patch
View File

@ -15,11 +15,9 @@ Signed-off-by: Tim Harvey <tharvey@gateworks.com>
drivers/gpio/gpio-thunderx.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpio/gpio-thunderx.c b/drivers/gpio/gpio-thunderx.c
index 715371b..feda2a2 100644
--- a/drivers/gpio/gpio-thunderx.c
+++ b/drivers/gpio/gpio-thunderx.c
@@ -363,15 +363,18 @@ static int thunderx_gpio_irq_request_resources(struct irq_data *data)
@@ -363,15 +363,18 @@ static int thunderx_gpio_irq_request_res
{
struct thunderx_line *txline = irq_data_get_irq_chip_data(data);
struct thunderx_gpio *txgpio = txline->txgpio;
@ -41,6 +39,3 @@ index 715371b..feda2a2 100644
return r;
}
--
2.7.4

9
target/linux/octeontx/patches-5.4/0003-can-mcp251x-convert-to-half-duplex-SPI.patch
View File

@ -12,11 +12,9 @@ Signed-off-by: Tim Harvey <tharvey@gateworks.com>
drivers/net/can/spi/mcp251x.c | 15 ++++++++-------
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/net/can/spi/mcp251x.c b/drivers/net/can/spi/mcp251x.c
index bb20a9b..dc0574a 100644
--- a/drivers/net/can/spi/mcp251x.c
+++ b/drivers/net/can/spi/mcp251x.c
@@ -291,23 +291,23 @@ static u8 mcp251x_read_reg(struct spi_device *spi, u8 reg)
@@ -291,23 +291,23 @@ static u8 mcp251x_read_reg(struct spi_de
priv->spi_tx_buf[0] = INSTRUCTION_READ;
priv->spi_tx_buf[1] = reg;
@ -45,7 +43,7 @@ index bb20a9b..dc0574a 100644
}
static void mcp251x_write_reg(struct spi_device *spi, u8 reg, u8 val)
@@ -398,8 +398,9 @@ static void mcp251x_hw_rx_frame(struct spi_device *spi, u8 *buf,
@@ -398,8 +398,9 @@ static void mcp251x_hw_rx_frame(struct s
buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i);
} else {
priv->spi_tx_buf[RXBCTRL_OFF] = INSTRUCTION_READ_RXB(buf_idx);
@ -57,6 +55,3 @@ index bb20a9b..dc0574a 100644
}
}
--
2.7.4