mirror of
https://git.openwrt.org/openwrt/openwrt.git
synced 2024-11-18 14:47:46 +01:00
atheros: USB support
SVN-Revision: 11113
This commit is contained in:
Matteo Croce
parent
6ba929a047
commit
c8d30d5f09
@ -9,9 +9,9 @@ include $(TOPDIR)/rules.mk
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ARCH:=mips
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BOARD:=atheros
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BOARDNAME:=Atheros 231x/5312
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FEATURES:=squashfs jffs2
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FEATURES:=squashfs jffs2 pci usb
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LINUX_VERSION:=2.6.23.16
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LINUX_VERSION:=2.6.25.1
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include $(INCLUDE_DIR)/target.mk
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@ -10,8 +10,11 @@ CONFIG_ARCH_SUSPEND_POSSIBLE=y
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CONFIG_ATHEROS=y
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CONFIG_ATHEROS_AR5312=y
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CONFIG_ATHEROS_AR5315=y
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CONFIG_ATHEROS_AR5315_PCI=y
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# CONFIG_ATM is not set
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# CONFIG_ATMEL is not set
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CONFIG_BASE_SMALL=0
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# CONFIG_BCM43XX is not set
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# CONFIG_BCM47XX is not set
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CONFIG_BITREVERSE=y
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# CONFIG_BROADCOM_PHY is not set
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@ -52,6 +55,7 @@ CONFIG_CRYPTO_AEAD=m
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CONFIG_CRYPTO_AUTHENC=m
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CONFIG_CRYPTO_GF128MUL=m
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CONFIG_CSRC_R4K=y
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CONFIG_DEVPORT=y
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# CONFIG_DM9000 is not set
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CONFIG_DMA_NEED_PCI_MAP_STATE=y
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CONFIG_DMA_NONCOHERENT=y
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@ -71,7 +75,9 @@ CONFIG_HAVE_IDE=y
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# CONFIG_HAVE_KPROBES is not set
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# CONFIG_HAVE_KRETPROBES is not set
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CONFIG_HAVE_OPROFILE=y
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# CONFIG_HERMES is not set
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# CONFIG_HOSTAP is not set
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CONFIG_HW_HAS_PCI=y
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CONFIG_HW_RANDOM=y
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# CONFIG_I2C is not set
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# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
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@ -80,8 +86,9 @@ CONFIG_HW_RANDOM=y
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# CONFIG_IBM_NEW_EMAC_ZMII is not set
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CONFIG_ICPLUS_PHY=y
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# CONFIG_IDE is not set
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# CONFIG_IEEE80211 is not set
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CONFIG_INITRAMFS_SOURCE=""
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# CONFIG_IPW2100 is not set
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# CONFIG_IPW2200 is not set
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CONFIG_IRQ_CPU=y
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# CONFIG_LEDS_ALIX is not set
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# CONFIG_LEDS_GPIO is not set
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@ -94,6 +101,7 @@ CONFIG_LZO_DECOMPRESS=m
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# CONFIG_MACH_VR41XX is not set
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# CONFIG_MDIO_BITBANG is not set
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# CONFIG_MEMSTICK is not set
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CONFIG_MII=m
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CONFIG_MIPS=y
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# CONFIG_MIPS_ATLAS is not set
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# CONFIG_MIPS_COBALT is not set
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@ -143,12 +151,14 @@ CONFIG_MTD_MAP_BANK_WIDTH_4=y
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# CONFIG_MTD_ONENAND is not set
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# CONFIG_MTD_OTP is not set
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CONFIG_MTD_PARTITIONS=y
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# CONFIG_MTD_PCI is not set
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# CONFIG_MTD_PHRAM is not set
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CONFIG_MTD_PHYSMAP=y
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CONFIG_MTD_PHYSMAP_BANKWIDTH=0
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CONFIG_MTD_PHYSMAP_LEN=0x0
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CONFIG_MTD_PHYSMAP_START=0x0
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# CONFIG_MTD_PLATRAM is not set
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# CONFIG_MTD_PMC551 is not set
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# CONFIG_MTD_RAM is not set
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CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-3
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CONFIG_MTD_REDBOOT_PARTS=y
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@ -156,17 +166,23 @@ CONFIG_MTD_REDBOOT_PARTS_READONLY=y
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# CONFIG_MTD_ROM is not set
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# CONFIG_MTD_SLRAM is not set
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CONFIG_MTD_SPIFLASH=y
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# CONFIG_NET_PCI is not set
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# CONFIG_NET_VENDOR_3COM is not set
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CONFIG_NEW_GPIO=y
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# CONFIG_NO_IOPORT is not set
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# CONFIG_PAGE_SIZE_16KB is not set
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CONFIG_PAGE_SIZE_4KB=y
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# CONFIG_PAGE_SIZE_64KB is not set
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# CONFIG_PAGE_SIZE_8KB is not set
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CONFIG_PCI=y
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# CONFIG_PCIPCWATCHDOG is not set
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CONFIG_PCI_DOMAINS=y
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CONFIG_PHYLIB=y
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# CONFIG_PMC_MSP is not set
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# CONFIG_PMC_YOSEMITE is not set
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# CONFIG_PNX8550_JBS is not set
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# CONFIG_PNX8550_STB810 is not set
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# CONFIG_PRISM54 is not set
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# CONFIG_QSEMI_PHY is not set
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# CONFIG_REALTEK_PHY is not set
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# CONFIG_RTC is not set
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@ -206,9 +222,11 @@ CONFIG_TICK_ONESHOT=y
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# CONFIG_TOSHIBA_RBTX4927 is not set
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# CONFIG_TOSHIBA_RBTX4938 is not set
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CONFIG_TRAD_SIGNALS=y
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# CONFIG_USB_ARCH_HAS_EHCI is not set
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# CONFIG_USB_ARCH_HAS_HCD is not set
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# CONFIG_USB_ARCH_HAS_OHCI is not set
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CONFIG_USB=m
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# CONFIG_USBPCWATCHDOG is not set
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# CONFIG_USB_EHCI_HCD is not set
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# CONFIG_USB_R8A66597_HCD is not set
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# CONFIG_USB_UHCI_HCD is not set
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# CONFIG_VGASTATE is not set
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CONFIG_VIDEO_V4L2_COMMON=m
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CONFIG_ZONE_DMA_FLAG=0
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@ -1,4 +1,3 @@
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config ATHEROS_AR5312
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bool "Atheros 5312/2312+ support"
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depends on ATHEROS
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@ -7,7 +6,22 @@ config ATHEROS_AR5312
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config ATHEROS_AR5315
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bool "Atheros 5315/2315+ support"
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depends on ATHEROS
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select DMA_NONCOHERENT
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select CEVT_R4K
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select CSRC_R4K
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select IRQ_CPU
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select SYS_HAS_CPU_MIPS32_R1
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select SYS_SUPPORTS_32BIT_KERNEL
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select SYS_SUPPORTS_BIG_ENDIAN
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select GENERIC_GPIO
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default y
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config ATHEROS_AR5315_PCI
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bool "PCI support"
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select HW_HAS_PCI
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select PCI
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select USB_ARCH_HAS_HCD
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select USB_ARCH_HAS_OHCI
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select USB_ARCH_HAS_EHCI
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depends on ATHEROS_AR5315
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default n
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@ -9,3 +9,4 @@
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#
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obj-y := board.o irq.o
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obj-$(CONFIG_ATHEROS_AR5315_PCI) += pci.o
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@ -60,6 +60,10 @@ asmlinkage void ar5315_irq_dispatch(void)
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do_IRQ(AR5315_IRQ_WLAN0_INTRS);
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else if (pending & CAUSEF_IP4)
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do_IRQ(AR5315_IRQ_ENET0_INTRS);
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#ifdef CONFIG_PCI
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else if (pending & CAUSEF_IP5)
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ar5315_pci_irq(AR5315_IRQ_LCBUS_PCI);
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#endif
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else if (pending & CAUSEF_IP2) {
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unsigned int ar531x_misc_intrs = sysRegRead(AR5315_ISR) & sysRegRead(AR5315_IMR);
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@ -81,6 +85,30 @@ asmlinkage void ar5315_irq_dispatch(void)
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do_IRQ(AR531X_IRQ_CPU_CLOCK);
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}
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#ifdef CONFIG_PCI
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static inline void pci_abort_irq(void)
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{
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sysRegWrite(AR5315_PCI_INT_STATUS, AR5315_PCI_ABORT_INT);
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(void)sysRegRead(AR5315_PCI_INT_STATUS); /* flush write to hardware */
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}
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static inline void pci_ack_irq(void)
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{
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sysRegWrite(AR5315_PCI_INT_STATUS, AR5315_PCI_EXT_INT);
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(void)sysRegRead(AR5315_PCI_INT_STATUS); /* flush write to hardware */
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}
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void ar5315_pci_irq(int irq)
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{
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if (sysRegRead(AR5315_PCI_INT_STATUS) == AR5315_PCI_ABORT_INT)
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pci_abort_irq();
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else {
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do_IRQ(irq);
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pci_ack_irq();
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}
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}
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#endif
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static void ar5315_gpio_intr_enable(unsigned int irq)
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{
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u32 gpio, mask;
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253
target/linux/atheros/files/arch/mips/atheros/ar5315/pci.c
Normal file
253
target/linux/atheros/files/arch/mips/atheros/ar5315/pci.c
Normal file
@ -0,0 +1,253 @@
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/*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/mm.h>
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#include <linux/spinlock.h>
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#include <linux/delay.h>
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#include <linux/irq.h>
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#include <asm/paccess.h>
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#include <asm/irq_cpu.h>
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#include <asm/io.h>
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#include "ar531x.h"
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#define AR531X_MEM_BASE 0x80800000UL
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#define AR531X_MEM_SIZE 0x00ffffffUL
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#define AR531X_IO_SIZE 0x00007fffUL
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#define IDSEL_SHIFT 13
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static spinlock_t ar531x_pci_lock = SPIN_LOCK_UNLOCKED;
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static u32 cfgaddr;
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static int config_access(int busno, int dev, int func, int where, int size, u32 ptr, int write)
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{
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u32 address; /* Address to read from */
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u32 reg;
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unsigned long flags;
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int ret = -1;
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if ((busno != 0) || (dev > 3) || (func > 2))
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return ret;
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spin_lock_irqsave(&ar531x_pci_lock, flags);
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/* Select Configuration access */
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reg = sysRegRead(AR5315_PCI_MISC_CONFIG);
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reg |= AR5315_PCIMISC_CFG_SEL;
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sysRegWrite(AR5315_PCI_MISC_CONFIG, reg);
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(void)sysRegRead(AR5315_PCI_MISC_CONFIG);
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address = (u32)cfgaddr + (1 << (IDSEL_SHIFT + dev)) + (func << 8) + where;
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if (size == 1)
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address ^= 0x3;
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else if (size == 2)
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address ^= 0x2;
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if (write) {
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if (size == 1)
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ret = put_dbe(ptr, (u8 *) address);
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else if (size == 2)
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ret = put_dbe(ptr, (u16 *) address);
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else if (size == 4)
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ret = put_dbe(ptr, (u32 *) address);
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} else {
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if (size == 1)
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ret = get_dbe(*((u32 *)ptr), (u8 *) address);
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else if (size == 2)
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ret = get_dbe(*((u32 *)ptr), (u16 *) address);
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else if (size == 4)
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ret = get_dbe(*((u32 *)ptr), (u32 *) address);
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}
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/* Select Memory access */
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reg = sysRegRead(AR5315_PCI_MISC_CONFIG);
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reg &= ~AR5315_PCIMISC_CFG_SEL;
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sysRegWrite(AR5315_PCI_MISC_CONFIG, reg);
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(void)sysRegRead(AR5315_PCI_MISC_CONFIG);
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spin_unlock_irqrestore(&ar531x_pci_lock, flags);
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if (ret) {
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*((u32 *)ptr) = 0xffffffff;
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static int ar531x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * value)
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{
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return config_access(bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size, (u32) value, 0);
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}
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static int ar531x_pci_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
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{
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return config_access(bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size, value, 1);
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}
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struct pci_ops ar531x_pci_ops = {
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.read = ar531x_pci_read,
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.write = ar531x_pci_write,
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};
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static struct resource ar531x_mem_resource = {
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.name = "AR531x PCI MEM",
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.start = AR531X_MEM_BASE,
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.end = AR531X_MEM_BASE + AR531X_MEM_SIZE - AR531X_IO_SIZE - 1,
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.flags = IORESOURCE_MEM,
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};
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static struct resource ar531x_io_resource = {
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.name = "AR531x PCI I/O",
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.start = 0,
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.end = AR531X_IO_SIZE,
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.flags = IORESOURCE_IO,
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};
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struct pci_controller ar531x_pci_controller = {
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.pci_ops = &ar531x_pci_ops,
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.mem_resource = &ar531x_mem_resource,
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.io_resource = &ar531x_io_resource,
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};
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int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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return AR5315_IRQ_LCBUS_PCI;
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}
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int pcibios_plat_dev_init(struct pci_dev *dev)
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{
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u32 reg;
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pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 5);
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pci_write_config_word(dev, 0x40, 0);
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/* Clear any pending Abort or external Interrupts
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* and enable interrupt processing */
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reg = sysRegRead(AR5315_PCI_INTEN_REG);
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reg &= ~AR5315_PCI_INT_ENABLE;
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sysRegWrite(AR5315_PCI_INTEN_REG, reg);
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reg = sysRegRead(AR5315_PCI_INT_STATUS);
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reg |= (AR5315_PCI_ABORT_INT | AR5315_PCI_EXT_INT);
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sysRegWrite(AR5315_PCI_INT_STATUS, reg);
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reg = sysRegRead(AR5315_PCI_INT_MASK);
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reg |= (AR5315_PCI_EXT_INT | AR5315_PCI_ABORT_INT);
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sysRegWrite(AR5315_PCI_INT_MASK, reg);
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reg = sysRegRead(AR5315_PCI_INTEN_REG);
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reg |= AR5315_PCI_INT_ENABLE;
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sysRegWrite(AR5315_PCI_INTEN_REG, reg);
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return 0;
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}
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static void ar5315_pci_fixup(struct pci_dev *dev)
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{
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struct pci_bus *bus = dev->bus;
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if ((PCI_SLOT(dev->devfn) != 3) || (PCI_FUNC(dev->devfn) != 0) || (bus->number != 0))
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return;
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#define _DEV bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn)
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printk("PCI: fixing up device %d,%d,%d\n", _DEV);
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/* fix up mbars */
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config_access(_DEV, PCI_BASE_ADDRESS_0, 4, HOST_PCI_MBAR0, 1);
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config_access(_DEV, PCI_BASE_ADDRESS_1, 4, HOST_PCI_MBAR1, 1);
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config_access(_DEV, PCI_BASE_ADDRESS_2, 4, HOST_PCI_MBAR2, 1);
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config_access(_DEV, PCI_COMMAND, 4,
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PCI_COMMAND_MEMORY|PCI_COMMAND_MASTER|PCI_COMMAND_SPECIAL|
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PCI_COMMAND_INVALIDATE|PCI_COMMAND_PARITY|PCI_COMMAND_SERR|
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PCI_COMMAND_FAST_BACK, 1);
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#undef _DEV
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, ar5315_pci_fixup);
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int __init ar5315_pci_init(void)
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{
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u32 reg;
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printk("AR531x PCI init... ");
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cfgaddr = (u32) ioremap_nocache(0x80000000, 1*1024*1024); /* Remap PCI config space */
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set_io_port_base((unsigned long) ioremap_nocache(AR531X_MEM_BASE + AR531X_IO_SIZE - 1, AR531X_IO_SIZE)); /* PCI I/O space */
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reg = sysRegRead(AR5315_RESET);
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sysRegWrite(AR5315_RESET, reg | AR5315_RESET_PCIDMA);
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udelay(10*1000);
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sysRegWrite(AR5315_RESET, reg & ~AR5315_RESET_PCIDMA);
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sysRegRead(AR5315_RESET); /* read after */
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udelay(10*1000);
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reg = sysRegRead(AR5315_ENDIAN_CTL);
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reg |= AR5315_CONFIG_PCIAHB | AR5315_CONFIG_PCIAHB_BRIDGE;
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sysRegWrite(AR5315_ENDIAN_CTL, reg);
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reg = sysRegRead(AR5315_PCICLK);
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reg = 4;
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sysRegWrite(AR5315_PCICLK, reg);
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reg = sysRegRead(AR5315_AHB_ARB_CTL);
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reg |= (ARB_PCI);
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sysRegWrite(AR5315_AHB_ARB_CTL, reg);
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reg = sysRegRead(AR5315_IF_CTL);
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reg &= ~(IF_PCI_CLK_MASK | IF_MASK);
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reg |= (IF_PCI | IF_PCI_HOST | IF_PCI_INTR | (IF_PCI_CLK_OUTPUT_CLK << IF_PCI_CLK_SHIFT));
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sysRegWrite(AR5315_IF_CTL, reg);
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/* Reset the PCI bus by setting bits 5-4 in PCI_MCFG */
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reg = sysRegRead(AR5315_PCI_MISC_CONFIG);
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reg &= ~(AR5315_PCIMISC_RST_MODE);
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reg |= AR5315_PCIRST_LOW;
|
||||
sysRegWrite(AR5315_PCI_MISC_CONFIG, reg);
|
||||
|
||||
/* wait for 100 ms */
|
||||
udelay(100*1000);
|
||||
|
||||
/* Bring the PCI out of reset */
|
||||
reg = sysRegRead(AR5315_PCI_MISC_CONFIG);
|
||||
reg &= ~(AR5315_PCIMISC_RST_MODE);
|
||||
reg |= (AR5315_PCIRST_HIGH | AR5315_PCICACHE_DIS | 0x8);
|
||||
sysRegWrite(AR5315_PCI_MISC_CONFIG, reg);
|
||||
|
||||
sysRegWrite(AR5315_PCI_UNCACHE_CFG,
|
||||
0x1E | /* 1GB uncached */
|
||||
(1 << 5) | /* Enable uncached */
|
||||
(0x2 << 30) /* Base: 0x80000000 */
|
||||
);
|
||||
(void)sysRegRead(AR5315_PCI_UNCACHE_CFG); /* flush */
|
||||
|
||||
udelay(500*1000);
|
||||
|
||||
register_pci_controller(&ar531x_pci_controller);
|
||||
|
||||
printk("done\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
arch_initcall(ar5315_pci_init);
|
||||
@ -10,11 +10,7 @@
|
||||
#ifndef __ASM_MACH_GENERIC_DMA_COHERENCE_H
|
||||
#define __ASM_MACH_GENERIC_DMA_COHERENCE_H
|
||||
|
||||
#if 0
|
||||
#define PCI_DMA_OFFSET 0x20000000
|
||||
#else
|
||||
#define PCI_DMA_OFFSET 0x00000000
|
||||
#endif
|
||||
|
||||
struct device;
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user