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Code Issues

ramips: add back the missing periph clock for Ralink RT3883

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periph clock is the parent clock of some other clocks.

Link: https://lore.kernel.org/all/CAMhs-H_NS-n2tx5SZpCMiVZtBFzX_nTa_vnS8We0UevkwFq93Q@mail.gmail.com/
Signed-off-by: Shiji Yang <yangshiji66@qq.com>
Link: https://github.com/openwrt/openwrt/pull/16318
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This commit is contained in:
Shiji Yang 2024-08-06 20:52:55 +08:00 committed by Hauke Mehrtens
parent 285f87d2c7
commit 656c9847d5
2 changed files with 55 additions and 10 deletions
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20
target/linux/ramips/dts/rt3883.dtsi
View File

@ -51,7 +51,7 @@
compatible = "ralink,rt2880-timer"; compatible = "ralink,rt2880-timer";
reg = <0x100 0x20>; reg = <0x100 0x20>;
clocks = <&sysc 3>; clocks = <&sysc 4>;
interrupt-parent = <&intc>; interrupt-parent = <&intc>;
interrupts = <1>; interrupts = <1>;
@ -61,7 +61,7 @@
compatible = "ralink,rt2880-wdt"; compatible = "ralink,rt2880-wdt";
reg = <0x120 0x10>; reg = <0x120 0x10>;
clocks = <&sysc 4>; clocks = <&sysc 5>;
resets = <&sysc 8>; resets = <&sysc 8>;
reset-names = "wdt"; reset-names = "wdt";
@ -93,7 +93,7 @@
compatible = "ralink,rt3883-uart", "ralink,rt2880-uart", "ns16550a"; compatible = "ralink,rt3883-uart", "ralink,rt2880-uart", "ns16550a";
reg = <0x500 0x100>; reg = <0x500 0x100>;
clocks = <&sysc 5>; clocks = <&sysc 6>;
resets = <&sysc 12>; resets = <&sysc 12>;
@ -170,7 +170,7 @@
compatible = "ralink,rt2880-i2c"; compatible = "ralink,rt2880-i2c";
reg = <0x900 0x100>; reg = <0x900 0x100>;
clocks = <&sysc 6>; clocks = <&sysc 7>;
resets = <&sysc 16>; resets = <&sysc 16>;
reset-names = "i2c"; reset-names = "i2c";
@ -188,7 +188,7 @@
compatible = "ralink,rt3883-i2s"; compatible = "ralink,rt3883-i2s";
reg = <0xa00 0x100>; reg = <0xa00 0x100>;
clocks = <&sysc 7>; clocks = <&sysc 8>;
resets = <&sysc 17>; resets = <&sysc 17>;
reset-names = "i2s"; reset-names = "i2s";
@ -212,7 +212,7 @@
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clocks = <&sysc 8>; clocks = <&sysc 9>;
resets = <&sysc 18>; resets = <&sysc 18>;
reset-names = "spi"; reset-names = "spi";
@ -229,7 +229,7 @@
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clocks = <&sysc 9>; clocks = <&sysc 10>;
resets = <&sysc 18>; resets = <&sysc 18>;
reset-names = "spi"; reset-names = "spi";
@ -244,7 +244,7 @@
compatible = "ralink,rt3883-uart", "ralink,rt2880-uart", "ns16550a"; compatible = "ralink,rt3883-uart", "ralink,rt2880-uart", "ns16550a";
reg = <0xc00 0x100>; reg = <0xc00 0x100>;
clocks = <&sysc 10>; clocks = <&sysc 11>;
resets = <&sysc 19>; resets = <&sysc 19>;
@ -326,7 +326,7 @@
#size-cells = <0>; #size-cells = <0>;
reg = <0x10100000 0x10000>; reg = <0x10100000 0x10000>;
clocks = <&sysc 11>; clocks = <&sysc 12>;
resets = <&sysc 21>; resets = <&sysc 21>;
reset-names = "fe"; reset-names = "fe";
@ -446,7 +446,7 @@
compatible = "ralink,rt3883-wmac", "ralink,rt2880-wmac"; compatible = "ralink,rt3883-wmac", "ralink,rt2880-wmac";
reg = <0x10180000 0x40000>; reg = <0x10180000 0x40000>;
clocks = <&sysc 12>; clocks = <&sysc 13>;
interrupt-parent = <&cpuintc>; interrupt-parent = <&cpuintc>;
interrupts = <6>; interrupts = <6>;

45
target/linux/ramips/patches-6.6/100-clk-ralink-mtmips-fix-clock-plan-for-Ralink-SoC-RT3883.patch Normal file
View File

@ -0,0 +1,45 @@
Subject: [PATCH] clk: ralink: mtmips: fix clock plan for Ralink SoC RT3883
Date: Tue, 6 Aug 2024 16:29:02 +0200
Message-Id: <20240806142902.224164-1-sergio.paracuellos@gmail.com>
Clock plan for Ralink SoC RT3883 needs an extra 'periph' clock to properly
set some peripherals that has this clock as their parent. When this driver
was mainlined we could not find any active users of this SoC so we cannot
perform any real tests for it. Now, one user of a Belkin f9k1109 version 1
device which uses this SoC appear and reported some issues in openWRT:
- https://github.com/openwrt/openwrt/issues/16054
The peripherals that are wrong are 'uart', 'i2c', 'i2s' and 'uartlite' which
has a not defined 'periph' clock as parent. Hence, introduce it to have a
properly working clock plan for this SoC.
Fixes: 6f3b15586eef ("clk: ralink: add clock and reset driver for MTMIPS SoCs")
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
drivers/clk/ralink/clk-mtmips.c | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
--- a/drivers/clk/ralink/clk-mtmips.c
+++ b/drivers/clk/ralink/clk-mtmips.c
@@ -267,6 +267,11 @@ static struct mtmips_clk_fixed rt305x_fi
CLK_FIXED("xtal", NULL, 40000000)
};
+static struct mtmips_clk_fixed rt3383_fixed_clocks[] = {
+ CLK_FIXED("xtal", NULL, 40000000),
+ CLK_FIXED("periph", "xtal", 40000000)
+};
+
static struct mtmips_clk_fixed rt3352_fixed_clocks[] = {
CLK_FIXED("periph", "xtal", 40000000)
};
@@ -779,8 +784,8 @@ static const struct mtmips_clk_data rt33
static const struct mtmips_clk_data rt3883_clk_data = {
.clk_base = rt3883_clks_base,
.num_clk_base = ARRAY_SIZE(rt3883_clks_base),
- .clk_fixed = rt305x_fixed_clocks,
- .num_clk_fixed = ARRAY_SIZE(rt305x_fixed_clocks),
+ .clk_fixed = rt3383_fixed_clocks,
+ .num_clk_fixed = ARRAY_SIZE(rt3383_fixed_clocks),
.clk_factor = NULL,
.num_clk_factor = 0,
.clk_periph = rt5350_pherip_clks,