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Adm5120 NAPI polling support and fixes by Thomas Langer and Friedrich Beckmann
SVN-Revision: 8013
This commit is contained in:
Florian Fainelli
parent
0e07409d92
commit
62e1634ed9
@ -5,6 +5,12 @@
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*
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* Inspiration for this driver came from the original ADMtek 2.4
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* driver, Copyright ADMtek Inc.
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*
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* NAPI extensions by Thomas Langer (Thomas.Langer@infineon.com)
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* and Friedrich Beckmann (Friedrich.Beckmann@infineon.com), 2007
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*
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* TODO: Add support of high prio queues (currently disabled)
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*
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*/
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#include <linux/autoconf.h>
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#include <linux/module.h>
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@ -48,6 +54,9 @@ static unsigned char bw_matrix[SW_DEVS] = {
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static int adm5120_nrdevs;
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static struct net_device *adm5120_devs[SW_DEVS];
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/* Lookup table port -> device */
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static struct net_device *adm5120_port[SW_DEVS];
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static struct adm5120_dma
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adm5120_dma_txh_v[ADM5120_DMA_TXH] __attribute__((aligned(16))),
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adm5120_dma_txl_v[ADM5120_DMA_TXL] __attribute__((aligned(16))),
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@ -62,13 +71,9 @@ static struct sk_buff
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*adm5120_skb_rxl[ADM5120_DMA_RXL],
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*adm5120_skb_txh[ADM5120_DMA_TXH],
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*adm5120_skb_txl[ADM5120_DMA_TXL];
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static int adm5120_rxhi = 0;
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static int adm5120_rxli = 0;
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/* We don't use high priority tx for now */
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/*static int adm5120_txhi = 0;*/
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static int adm5120_txli = 0;
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static int adm5120_txhit = 0;
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static int adm5120_txlit = 0;
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/*static int adm5120_txhi = 0;*/
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static int adm5120_if_open = 0;
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static inline void adm5120_set_reg(unsigned int reg, unsigned long val)
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@ -81,47 +86,50 @@ static inline unsigned long adm5120_get_reg(unsigned int reg)
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return *(volatile unsigned long*)(SW_BASE+reg);
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}
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static inline void adm5120_rxfixup(struct adm5120_dma *dma,
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struct sk_buff **skbl, int num)
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static inline void adm5120_rx_dma_update(struct adm5120_dma *dma,
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struct sk_buff *skb, int end)
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{
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int i;
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/* Resubmit the entire ring */
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for (i=0; i<num; i++) {
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dma[i].status = 0;
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dma[i].cntl = 0;
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dma[i].len = ADM5120_DMA_RXSIZE;
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dma[i].data = ADM5120_DMA_ADDR(skbl[i]->data) |
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ADM5120_DMA_OWN | (i==num-1 ? ADM5120_DMA_RINGEND : 0);
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}
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dma->status = 0;
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dma->cntl = 0;
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dma->len = ADM5120_DMA_RXSIZE;
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dma->data = ADM5120_DMA_ADDR(skb->data) |
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ADM5120_DMA_OWN | (end ? ADM5120_DMA_RINGEND : 0);
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}
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static inline void adm5120_rx(struct adm5120_dma *dma, struct sk_buff **skbl,
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int *index, int num)
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static int adm5120_rx(struct net_device *dev,int *budget)
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{
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struct sk_buff *skb, *skbn;
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struct adm5120_sw *priv;
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struct net_device *dev;
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int port, vlan, len;
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struct net_device *cdev;
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struct adm5120_dma *dma;
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int port, len, quota;
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while (!(dma[*index].data & ADM5120_DMA_OWN)) {
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port = (dma[*index].status & ADM5120_DMA_PORTID);
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quota = min(dev->quota, *budget);
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dma = &adm5120_dma_rxl[adm5120_rxli];
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while (!(dma->data & ADM5120_DMA_OWN) && quota) {
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port = (dma->status & ADM5120_DMA_PORTID);
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port >>= ADM5120_DMA_PORTSHIFT;
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for (vlan = 0; vlan < adm5120_nrdevs; vlan++) {
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if ((1<<port) & vlan_matrix[vlan])
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break;
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cdev = adm5120_port[port];
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if (cdev != dev) { /* The current packet belongs to a different device */
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if ((cdev==NULL) || !netif_running(cdev)) {
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/* discard (update with old skb) */
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skb = skbn = NULL;
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goto rx_skip;
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}
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else {
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netif_rx_schedule(cdev);/* Start polling next device */
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return 1; /* return 1 -> More packets to process */
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}
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}
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if (vlan == adm5120_nrdevs)
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vlan = 0;
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dev = adm5120_devs[vlan];
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skb = skbl[*index];
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len = (dma[*index].status & ADM5120_DMA_LEN);
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skb = adm5120_skb_rxl[adm5120_rxli];
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len = (dma->status & ADM5120_DMA_LEN);
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len >>= ADM5120_DMA_LENSHIFT;
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len -= ETH_FCS;
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priv = netdev_priv(dev);
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if (len <= 0 || len > ADM5120_DMA_RXSIZE ||
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dma[*index].status & ADM5120_DMA_FCSERR) {
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dma->status & ADM5120_DMA_FCSERR) {
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priv->stats.rx_errors++;
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skbn = NULL;
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} else {
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@ -133,69 +141,80 @@ static inline void adm5120_rx(struct adm5120_dma *dma, struct sk_buff **skbl,
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skb->ip_summed = CHECKSUM_UNNECESSARY;
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dev->last_rx = jiffies;
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priv->stats.rx_packets++;
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priv->stats.rx_bytes+=len;
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skb_reserve(skbn, 2);
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skbl[*index] = skbn;
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priv->stats.rx_bytes += len;
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skb_reserve(skbn, NET_IP_ALIGN);
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adm5120_skb_rxl[adm5120_rxli] = skbn;
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} else {
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printk(KERN_INFO "%s recycling!\n", dev->name);
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}
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}
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rx_skip:
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adm5120_rx_dma_update(&adm5120_dma_rxl[adm5120_rxli],
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adm5120_skb_rxl[adm5120_rxli],
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(ADM5120_DMA_RXL-1==adm5120_rxli));
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if (ADM5120_DMA_RXL == ++adm5120_rxli)
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adm5120_rxli = 0;
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dma = &adm5120_dma_rxl[adm5120_rxli];
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if (skbn){
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netif_receive_skb(skb);
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dev->quota--;
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(*budget)--;
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quota--;
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}
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} /* while */
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/* If there are still packets to process, return 1 */
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if (quota){
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/* No more packets to process, so disable the polling and reenable the interrupts */
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netif_rx_complete(dev);
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adm5120_set_reg(ADM5120_INT_MASK,
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adm5120_get_reg(ADM5120_INT_MASK) &
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~(ADM5120_INT_RXL|ADM5120_INT_LFULL));
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return 0;
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dma[*index].status = 0;
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dma[*index].cntl = 0;
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dma[*index].len = ADM5120_DMA_RXSIZE;
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dma[*index].data = ADM5120_DMA_ADDR(skbl[*index]->data) |
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ADM5120_DMA_OWN |
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(num-1==*index ? ADM5120_DMA_RINGEND : 0);
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if (num == ++*index)
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*index = 0;
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if (skbn)
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netif_rx(skb);
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}
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}
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static inline void adm5120_tx(struct adm5120_dma *dma, struct sk_buff **skbl,
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int *index, int num)
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{
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while((dma[*index].data & ADM5120_DMA_OWN) == 0 && skbl[*index]) {
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dev_kfree_skb_irq(skbl[*index]);
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skbl[*index] = NULL;
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if (++*index == num)
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*index = 0;
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}
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return 1;
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}
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static irqreturn_t adm5120_sw_irq(int irq, void *dev_id)
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{
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unsigned long intreg;
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unsigned long intreg, intmask;
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int port;
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struct net_device *dev;
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adm5120_set_reg(ADM5120_INT_MASK,
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adm5120_get_reg(ADM5120_INT_MASK) | ADM5120_INTHANDLE);
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intmask = adm5120_get_reg(ADM5120_INT_MASK); /* Remember interrupt mask */
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adm5120_set_reg(ADM5120_INT_MASK, ADM5120_INTMASKALL); /* Disable interrupts */
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intreg = adm5120_get_reg(ADM5120_INT_ST);
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adm5120_set_reg(ADM5120_INT_ST, intreg);
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intreg = adm5120_get_reg(ADM5120_INT_ST); /* Read interrupt status */
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adm5120_set_reg(ADM5120_INT_ST, intreg); /* Clear interrupt status */
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if (intreg & ADM5120_INT_RXH)
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adm5120_rx(adm5120_dma_rxh, adm5120_skb_rxh, &adm5120_rxhi,
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ADM5120_DMA_RXH);
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if (intreg & ADM5120_INT_HFULL)
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adm5120_rxfixup(adm5120_dma_rxh, adm5120_skb_rxh,
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ADM5120_DMA_RXH);
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if (intreg & ADM5120_INT_RXL)
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adm5120_rx(adm5120_dma_rxl, adm5120_skb_rxl, &adm5120_rxli,
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ADM5120_DMA_RXL);
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if (intreg & ADM5120_INT_LFULL)
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adm5120_rxfixup(adm5120_dma_rxl, adm5120_skb_rxl,
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ADM5120_DMA_RXL);
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if (intreg & ADM5120_INT_TXH)
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adm5120_tx(adm5120_dma_txh, adm5120_skb_txh, &adm5120_txhit,
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ADM5120_DMA_TXH);
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if (intreg & ADM5120_INT_TXL)
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adm5120_tx(adm5120_dma_txl, adm5120_skb_txl, &adm5120_txlit,
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ADM5120_DMA_TXL);
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/* In NAPI operation the interrupts are disabled and the polling mechanism
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* is activated. The interrupts are finally enabled again in the polling routine.
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*/
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if (intreg & (ADM5120_INT_RXL|ADM5120_INT_LFULL)) {
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/* check rx buffer for port number */
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port = adm5120_dma_rxl[adm5120_rxli].status & ADM5120_DMA_PORTID;
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port >>= ADM5120_DMA_PORTSHIFT;
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dev = adm5120_port[port];
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if ((dev==NULL) || !netif_running(dev)) {
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/* discard (update with old skb) */
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adm5120_rx_dma_update(&adm5120_dma_rxl[adm5120_rxli],
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adm5120_skb_rxl[adm5120_rxli],
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(ADM5120_DMA_RXL-1==adm5120_rxli));
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if (ADM5120_DMA_RXL == ++adm5120_rxli)
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adm5120_rxli = 0;
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}
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else {
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netif_rx_schedule(dev);
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intmask |= (ADM5120_INT_RXL|ADM5120_INT_LFULL); /* Disable RX interrupts */
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}
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}
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#ifdef CONFIG_DEBUG
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if (intreg & ~(intmask))
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printk(KERN_INFO "adm5120sw: IRQ 0x%08X unexpected!\n", (unsigned int)(intreg & ~(intmask)));
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#endif
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adm5120_set_reg(ADM5120_INT_MASK,
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adm5120_get_reg(ADM5120_INT_MASK) & ~ADM5120_INTHANDLE);
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adm5120_set_reg(ADM5120_INT_MASK, intmask);
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return IRQ_HANDLED;
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}
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@ -203,11 +222,20 @@ static irqreturn_t adm5120_sw_irq(int irq, void *dev_id)
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static void adm5120_set_vlan(char *matrix)
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{
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unsigned long val;
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int vlan_port, port;
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val = matrix[0] + (matrix[1]<<8) + (matrix[2]<<16) + (matrix[3]<<24);
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adm5120_set_reg(ADM5120_VLAN_GI, val);
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val = matrix[4] + (matrix[5]<<8);
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adm5120_set_reg(ADM5120_VLAN_GII, val);
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/* Now set/update the port vs. device lookup table */
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for (port=0; port<SW_DEVS; port++) {
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for (vlan_port=0; vlan_port<SW_DEVS && !(matrix[vlan_port] & (0x00000001 << port)); vlan_port++);
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if (vlan_port <SW_DEVS)
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adm5120_port[port] = adm5120_devs[vlan_port];
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else
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adm5120_port[port] = NULL;
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}
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}
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static void adm5120_set_bw(char *matrix)
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@ -225,70 +253,143 @@ static void adm5120_set_bw(char *matrix)
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else
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adm5120_set_reg(ADM5120_BW_CTL1, val & ~0x8000000);
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printk(KERN_DEBUG "D: ctl0 0x%x, ctl1 0x%x\n",
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printk(KERN_DEBUG "D: ctl0 0x%lx, ctl1 0x%lx\n",
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adm5120_get_reg(ADM5120_BW_CTL0),
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adm5120_get_reg(ADM5120_BW_CTL1));
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}
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static int adm5120_sw_open(struct net_device *dev)
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{
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if (!adm5120_if_open++)
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adm5120_set_reg(ADM5120_INT_MASK,
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adm5120_get_reg(ADM5120_INT_MASK) & ~ADM5120_INTHANDLE);
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unsigned long val;
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int i;
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netif_start_queue(dev);
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if (!adm5120_if_open++) {
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/* enable interrupts on first open */
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adm5120_set_reg(ADM5120_INT_MASK,
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adm5120_get_reg(ADM5120_INT_MASK) &
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~(ADM5120_INT_RXL|ADM5120_INT_LFULL));
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}
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/* enable (additional) port */
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val = adm5120_get_reg(ADM5120_PORT_CONF0);
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for (i=0; i<SW_DEVS; i++) {
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if (dev == adm5120_devs[i])
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val &= ~vlan_matrix[i];
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}
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adm5120_set_reg(ADM5120_PORT_CONF0, val);
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return 0;
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}
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static int adm5120_sw_stop(struct net_device *dev)
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{
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unsigned long val;
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int i;
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if (!--adm5120_if_open) {
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adm5120_set_reg(ADM5120_INT_MASK, ADM5120_INTMASKALL);
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}
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/* disable port if not assigned to other devices */
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val = adm5120_get_reg(ADM5120_PORT_CONF0) | ADM5120_PORTDISALL;
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for (i=0; i<SW_DEVS; i++) {
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if ((dev != adm5120_devs[i]) && netif_running(adm5120_devs[i]))
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val &= ~vlan_matrix[i];
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}
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adm5120_set_reg(ADM5120_PORT_CONF0, val);
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netif_stop_queue(dev);
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if (!--adm5120_if_open)
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adm5120_set_reg(ADM5120_INT_MASK,
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adm5120_get_reg(ADM5120_INT_MASK) | ADM5120_INTMASKALL);
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return 0;
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}
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static int adm5120_sw_tx(struct sk_buff *skb, struct net_device *dev)
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{
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struct adm5120_dma *dma = adm5120_dma_txl;
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struct adm5120_dma *dma;
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struct sk_buff **skbl = adm5120_skb_txl;
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struct adm5120_sw *priv = netdev_priv(dev);
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int *index = &adm5120_txli;
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int num = ADM5120_DMA_TXL;
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int trigger = ADM5120_SEND_TRIG_L;
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unsigned long data;
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dev->trans_start = jiffies;
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if (dma[*index].data & ADM5120_DMA_OWN) {
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dma = &adm5120_dma_txl[adm5120_txli];
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if (dma->data & ADM5120_DMA_OWN) {
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/* We want to write a packet but the TX queue is still
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* occupied by the DMA. We are faster than the DMA... */
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dev_kfree_skb(skb);
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priv->stats.tx_dropped++;
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return 0;
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}
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dma[*index].data = ADM5120_DMA_ADDR(skb->data) | ADM5120_DMA_OWN;
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if (*index == num-1)
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dma[*index].data |= ADM5120_DMA_RINGEND;
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dma[*index].status =
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data = ADM5120_DMA_ADDR(skb->data) | ADM5120_DMA_OWN;
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if (adm5120_txli == ADM5120_DMA_TXL-1)
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data |= ADM5120_DMA_RINGEND;
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dma->status =
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((skb->len<ETH_ZLEN?ETH_ZLEN:skb->len) << ADM5120_DMA_LENSHIFT) |
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(0x1 << priv->port);
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dma[*index].len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
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dma->len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
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priv->stats.tx_packets++;
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priv->stats.tx_bytes += skb->len;
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skbl[*index]=skb;
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if (++*index == num)
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*index = 0;
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adm5120_set_reg(ADM5120_SEND_TRIG, trigger);
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/* free old skbs here instead of tx completion interrupt:
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* will hold some more memory allocated but reduces interrupts */
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if (skbl[adm5120_txli]){
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dev_kfree_skb(skbl[adm5120_txli]);
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}
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skbl[adm5120_txli] = skb;
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dma->data = data; /* Here we enable the buffer for the TX DMA machine */
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adm5120_set_reg(ADM5120_SEND_TRIG, ADM5120_SEND_TRIG_L);
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if (++adm5120_txli == ADM5120_DMA_TXL)
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adm5120_txli = 0;
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return 0;
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}
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static void adm5120_tx_timeout(struct net_device *dev)
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{
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netif_wake_queue(dev);
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printk(KERN_INFO "%s: TX timeout\n",dev->name);
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}
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static struct net_device_stats *adm5120_sw_stats(struct net_device *dev)
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{
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struct adm5120_sw *priv = netdev_priv(dev);
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int portmask;
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unsigned long adm5120_cpup_conf_reg;
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portmask = vlan_matrix[priv->port] & 0x3f;
|
||||
|
||||
adm5120_cpup_conf_reg = adm5120_get_reg(ADM5120_CPUP_CONF);
|
||||
|
||||
if (dev->flags & IFF_PROMISC)
|
||||
adm5120_cpup_conf_reg &= ~((portmask << ADM5120_DISUNSHIFT) & ADM5120_DISUNALL);
|
||||
else
|
||||
adm5120_cpup_conf_reg |= (portmask << ADM5120_DISUNSHIFT);
|
||||
|
||||
if (dev->flags & IFF_PROMISC || dev->flags & IFF_ALLMULTI || dev->mc_count)
|
||||
adm5120_cpup_conf_reg &= ~((portmask << ADM5120_DISMCSHIFT) & ADM5120_DISMCALL);
|
||||
else
|
||||
adm5120_cpup_conf_reg |= (portmask << ADM5120_DISMCSHIFT);
|
||||
|
||||
/* If there is any port configured to be in promiscuous mode, then the */
|
||||
/* Bridge Test Mode has to be activated. This will result in */
|
||||
/* transporting also packets learned in another VLAN to be forwarded */
|
||||
/* to the CPU. */
|
||||
/* The difficult scenario is when we want to build a bridge on the CPU.*/
|
||||
/* Assume we have port0 and the CPU port in VLAN0 and port1 and the */
|
||||
/* CPU port in VLAN1. Now we build a bridge on the CPU between */
|
||||
/* VLAN0 and VLAN1. Both ports of the VLANs are set in promisc mode. */
|
||||
/* Now assume a packet with ethernet source address 99 enters port 0 */
|
||||
/* It will be forwarded to the CPU because it is unknown. Then the */
|
||||
/* bridge in the CPU will send it to VLAN1 and it goes out at port 1. */
|
||||
/* When now a packet with ethernet destination address 99 comes in at */
|
||||
/* port 1 in VLAN1, then the switch has learned that this address is */
|
||||
/* located at port 0 in VLAN0. Therefore the switch will drop */
|
||||
/* this packet. In order to avoid this and to send the packet still */
|
||||
/* to the CPU, the Bridge Test Mode has to be activated. */
|
||||
|
||||
/* Check if there is any vlan in promisc mode. */
|
||||
if (~adm5120_cpup_conf_reg & ADM5120_DISUNALL)
|
||||
adm5120_cpup_conf_reg |= ADM5120_BTM; /* Set the BTM */
|
||||
else
|
||||
adm5120_cpup_conf_reg &= ~ADM5120_BTM; /* Disable the BTM */
|
||||
|
||||
adm5120_set_reg(ADM5120_CPUP_CONF,adm5120_cpup_conf_reg);
|
||||
|
||||
return &((struct adm5120_sw *)netdev_priv(dev))->stats;
|
||||
}
|
||||
|
||||
@ -390,33 +491,29 @@ static int adm5120_do_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void adm5120_dma_tx_init(struct adm5120_dma *dma, struct sk_buff **skb,
|
||||
static void adm5120_dma_tx_init(struct adm5120_dma *dma, struct sk_buff **skbl,
|
||||
int num)
|
||||
{
|
||||
memset(dma, 0, sizeof(struct adm5120_dma)*num);
|
||||
dma[num-1].data |= ADM5120_DMA_RINGEND;
|
||||
memset(skb, 0, sizeof(struct skb*)*num);
|
||||
memset(skbl, 0, sizeof(struct skb*)*num);
|
||||
}
|
||||
|
||||
static void adm5120_dma_rx_init(struct adm5120_dma *dma, struct sk_buff **skb,
|
||||
static void adm5120_dma_rx_init(struct adm5120_dma *dma, struct sk_buff **skbl,
|
||||
int num)
|
||||
{
|
||||
int i;
|
||||
|
||||
memset(dma, 0, sizeof(struct adm5120_dma)*num);
|
||||
for (i=0; i<num; i++) {
|
||||
skb[i] = dev_alloc_skb(ADM5120_DMA_RXSIZE+16);
|
||||
if (!skb[i]) {
|
||||
skbl[i] = dev_alloc_skb(ADM5120_DMA_RXSIZE+16);
|
||||
if (!skbl[i]) {
|
||||
i=num;
|
||||
break;
|
||||
}
|
||||
skb_reserve(skb[i], 2);
|
||||
dma[i].data = ADM5120_DMA_ADDR(skb[i]->data) | ADM5120_DMA_OWN;
|
||||
dma[i].cntl = 0;
|
||||
dma[i].len = ADM5120_DMA_RXSIZE;
|
||||
dma[i].status = 0;
|
||||
skb_reserve(skbl[i], NET_IP_ALIGN);
|
||||
adm5120_rx_dma_update(&dma[i], skbl[i], (num-1==i));
|
||||
}
|
||||
dma[i-1].data |= ADM5120_DMA_RINGEND;
|
||||
}
|
||||
|
||||
static int __init adm5120_sw_init(void)
|
||||
@ -433,7 +530,7 @@ static int __init adm5120_sw_init(void)
|
||||
adm5120_set_reg(ADM5120_CPUP_CONF,
|
||||
ADM5120_DISCCPUPORT | ADM5120_CRC_PADDING |
|
||||
ADM5120_DISUNALL | ADM5120_DISMCALL);
|
||||
adm5120_set_reg(ADM5120_PORT_CONF0, ADM5120_ENMC | ADM5120_ENBP);
|
||||
adm5120_set_reg(ADM5120_PORT_CONF0, ADM5120_ENMC | ADM5120_ENBP | ADM5120_PORTDISALL);
|
||||
|
||||
adm5120_set_reg(ADM5120_PHY_CNTL2, adm5120_get_reg(ADM5120_PHY_CNTL2) |
|
||||
ADM5120_AUTONEG | ADM5120_NORMAL | ADM5120_AUTOMDIX);
|
||||
@ -457,8 +554,6 @@ static int __init adm5120_sw_init(void)
|
||||
adm5120_set_reg(ADM5120_RECEIVE_HBADDR, KSEG1ADDR(adm5120_dma_rxh));
|
||||
adm5120_set_reg(ADM5120_RECEIVE_LBADDR, KSEG1ADDR(adm5120_dma_rxl));
|
||||
|
||||
adm5120_set_vlan(vlan_matrix);
|
||||
|
||||
for (i=0; i<adm5120_nrdevs; i++) {
|
||||
adm5120_devs[i] = alloc_etherdev(sizeof(struct adm5120_sw));
|
||||
if (!adm5120_devs[i]) {
|
||||
@ -481,6 +576,8 @@ static int __init adm5120_sw_init(void)
|
||||
dev->tx_timeout = adm5120_tx_timeout;
|
||||
dev->watchdog_timeo = ETH_TX_TIMEOUT;
|
||||
dev->set_mac_address = adm5120_sw_set_mac_address;
|
||||
dev->poll = adm5120_rx;
|
||||
dev->weight = 64;
|
||||
|
||||
memcpy(dev->dev_addr, adm5120_eth_macs[i], 6);
|
||||
adm5120_write_mac(dev);
|
||||
@ -491,6 +588,9 @@ static int __init adm5120_sw_init(void)
|
||||
}
|
||||
printk(KERN_INFO "%s: ADM5120 switch port%d\n", dev->name, i);
|
||||
}
|
||||
/* setup vlan/port mapping after devs are filled up */
|
||||
adm5120_set_vlan(vlan_matrix);
|
||||
|
||||
adm5120_set_reg(ADM5120_CPUP_CONF,
|
||||
ADM5120_CRC_PADDING | ADM5120_DISUNALL | ADM5120_DISMCALL);
|
||||
|
||||
|
||||
@ -13,14 +13,17 @@
|
||||
#define SW_BASE KSEG1ADDR(0x12000000)
|
||||
#define SW_DEVS 6
|
||||
|
||||
#define ETH_TX_TIMEOUT HZ/4
|
||||
#define ETH_TX_TIMEOUT HZ*400
|
||||
#define ETH_FCS 4;
|
||||
|
||||
#define ADM5120_CODE 0x00 /* CPU description */
|
||||
#define ADM5120_CODE_PQFP 0x20000000 /* package type */
|
||||
#define ADM5120_SW_CONF 0x20 /* Switch configuration register */
|
||||
#define ADM5120_SW_CONF_BPM 0x00300000 /* Mask for backpressure mode */
|
||||
#define ADM5120_CPUP_CONF 0x24 /* CPU port config */
|
||||
#define ADM5120_DISCCPUPORT 0x00000001 /* disable cpu port */
|
||||
#define ADM5120_CRC_PADDING 0x00000002 /* software crc */
|
||||
#define ADM5120_BTM 0x00000004 /* bridge test mode */
|
||||
#define ADM5120_DISUNSHIFT 9
|
||||
#define ADM5120_DISUNALL 0x00007e00 /* disable unknown from all */
|
||||
#define ADM5120_DISMCSHIFT 16
|
||||
@ -28,6 +31,7 @@
|
||||
#define ADM5120_PORT_CONF0 0x28
|
||||
#define ADM5120_ENMC 0x00003f00 /* Enable MC routing (ex cpu) */
|
||||
#define ADM5120_ENBP 0x003f0000 /* Enable Back Pressure */
|
||||
#define ADM5120_PORTDISALL 0x0000003F
|
||||
#define ADM5120_VLAN_GI 0x40 /* VLAN settings */
|
||||
#define ADM5120_VLAN_GII 0x44
|
||||
#define ADM5120_SEND_TRIG 0x48
|
||||
@ -81,10 +85,10 @@ struct adm5120_dma {
|
||||
#define ADM5120_DMA_LENSHIFT 16
|
||||
#define ADM5120_DMA_FCSERR 0x00000008
|
||||
|
||||
#define ADM5120_DMA_TXH 16
|
||||
#define ADM5120_DMA_TXH 2
|
||||
#define ADM5120_DMA_TXL 64
|
||||
#define ADM5120_DMA_RXH 16
|
||||
#define ADM5120_DMA_RXL 8
|
||||
#define ADM5120_DMA_RXH 2
|
||||
#define ADM5120_DMA_RXL 64
|
||||
|
||||
#define ADM5120_DMA_RXSIZE 1550
|
||||
#define ADM5120_DMA_EXTRA 20
|
||||
|
||||
Loading…
Reference in New Issue
Block a user