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mirror of https://git.openwrt.org/openwrt/openwrt.git synced 2024-10-18 13:29:16 +02:00

bcm53xx: MR32: replace i2c-gpio with SoC's i2c

During review of the MR32, Florian Fainelli pointed out that the
SoC has a real I2C-controller. Furthermore, the connected pins
(SDA and SCL) would line up perfectly for use. This patch swaps
out the the bitbanged i2c-gpio with the real deal.

Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
This commit is contained in:
Christian Lamparter 2020-09-12 22:28:38 +02:00
parent f5d071a508
commit 6102f883ce
3 changed files with 118 additions and 1 deletions

@ -318,7 +318,7 @@ TARGET_DEVICES += luxul_xwr-3150
define Device/meraki_mr32
DEVICE_VENDOR := Meraki
DEVICE_MODEL := MR32
DEVICE_PACKAGES := $(B43) kmod-i2c-bcm-iproc kmod-i2c-gpio kmod-eeprom-at24 \
DEVICE_PACKAGES := $(B43) kmod-i2c-bcm-iproc kmod-eeprom-at24 \
kmod-leds-pwm kmod-hwmon-ina2xx kmod-bluetooth
DEVICE_DTS := bcm53016-meraki-mr32
# Meraki FW r23 tries to resize the part.safe partition before it will

@ -0,0 +1,32 @@
From beda1bbdb19baa8319ed81fa370fe0c5b91d05df Mon Sep 17 00:00:00 2001
From: Florian Fainelli <f.fainelli@gmail.com>
Date: Tue, 26 Oct 2021 11:36:22 -0700
Subject: [PATCH] ARM: dts: BCM5301X: Fix I2C controller interrupt
The I2C interrupt controller line is off by 32 because the datasheet
describes interrupt inputs into the GIC which are for Shared Peripheral
Interrupts and are starting at offset 32. The ARM GIC binding expects
the SPI interrupts to be numbered from 0 relative to the SPI base.
Fixes: bb097e3e0045 ("ARM: dts: BCM5301X: Add I2C support to the DT")
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/arm/boot/dts/bcm5301x.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi
index f92089290ccd..ec5de636796e 100644
--- a/arch/arm/boot/dts/bcm5301x.dtsi
+++ b/arch/arm/boot/dts/bcm5301x.dtsi
@@ -408,7 +408,7 @@ uart2: serial@18008000 {
i2c0: i2c@18009000 {
compatible = "brcm,iproc-i2c";
reg = <0x18009000 0x50>;
- interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <100000>;
--
2.25.1

@ -0,0 +1,85 @@
From: Christian Lamparter <chunkeey@gmail.com>
Date: Sat, 12 Sep 2020 22:11:12 +0200
Subject: bcm53xx: Meraki MR32 use hw i2c
replace the i2c-gpio provided i2c functionality with the
hardware in the SoC. This can be activated once the
internal i2c works as well as the bit-banged i2c-gpio.
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
--- a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts
+++ b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts
@@ -85,40 +85,6 @@
max-brightness = <255>;
};
};
-
- i2c {
- /*
- * The platform provided I2C does not budge.
- * This is a replacement until I can figure
- * out what are the missing bits...
- */
-
- compatible = "i2c-gpio";
- sda-gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>;
- scl-gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>;
- i2c-gpio,delay-us = <10>; /* close to 100 kHz */
- #address-cells = <1>;
- #size-cells = <0>;
-
- current_sense: ina219@45 {
- compatible = "ti,ina219";
- reg = <0x45>;
- shunt-resistor = <60000>; /* = 60 mOhms */
- };
-
- eeprom: eeprom@50 {
- compatible = "atmel,24c64";
- reg = <0x50>;
- pagesize = <32>;
- read-only;
- #address-cells = <1>;
- #size-cells = <1>;
-
- mac_address: mac-address@66 {
- reg = <0x66 0x6>;
- };
- };
- };
};
&uart0 {
@@ -196,3 +168,31 @@
};
};
};
+
+&i2c0 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinmux_i2c>;
+
+ clock-frequency = <100000>;
+
+ current_sense: ina219@45 {
+ compatible = "ti,ina219";
+ reg = <0x45>;
+ shunt-resistor = <60000>; /* = 60 mOhms */
+ };
+
+ eeprom: eeprom@50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ pagesize = <32>;
+ read-only;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ mac_address: mac-address@66 {
+ reg = <0x66 0x6>;
+ };
+ };
+};