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ar71xx: ag71xx: simplify register access functions
SVN-Revision: 19949
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parent
e157281c5d
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@ -38,7 +38,7 @@
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#define ETH_FCS_LEN 4
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#define AG71XX_DRV_NAME "ag71xx"
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#define AG71XX_DRV_VERSION "0.5.26"
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#define AG71XX_DRV_VERSION "0.5.27"
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#define AG71XX_NAPI_WEIGHT 64
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#define AG71XX_OOM_REFILL (1 + HZ/10)
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@ -343,76 +343,56 @@ static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc)
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#define MII_CTRL_SPEED_100 1
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#define MII_CTRL_SPEED_1000 2
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static inline void ag71xx_wr(struct ag71xx *ag, unsigned reg, u32 value)
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static inline void ag71xx_check_reg_offset(struct ag71xx *ag, unsigned reg)
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{
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void __iomem *r;
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switch (reg) {
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case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
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case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
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r = ag->mac_base + reg;
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__raw_writel(value, r);
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/* flush write */
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(void) __raw_readl(r);
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break;
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default:
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BUG();
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}
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}
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static inline void ag71xx_wr(struct ag71xx *ag, unsigned reg, u32 value)
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{
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ag71xx_check_reg_offset(ag, reg);
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__raw_writel(value, ag->mac_base + reg);
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/* flush write */
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(void) __raw_readl(ag->mac_base + reg);
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}
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static inline u32 ag71xx_rr(struct ag71xx *ag, unsigned reg)
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{
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void __iomem *r;
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u32 ret;
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ag71xx_check_reg_offset(ag, reg);
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switch (reg) {
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case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
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case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
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r = ag->mac_base + reg;
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ret = __raw_readl(r);
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break;
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default:
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BUG();
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}
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return ret;
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return __raw_readl(ag->mac_base + reg);
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}
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static inline void ag71xx_sb(struct ag71xx *ag, unsigned reg, u32 mask)
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{
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void __iomem *r;
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switch (reg) {
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case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
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case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
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r = ag->mac_base + reg;
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__raw_writel(__raw_readl(r) | mask, r);
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ag71xx_check_reg_offset(ag, reg);
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/* flush write */
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(void)__raw_readl(r);
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break;
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default:
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BUG();
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}
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r = ag->mac_base + reg;
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__raw_writel(__raw_readl(r) | mask, r);
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/* flush write */
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(void)__raw_readl(r);
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}
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static inline void ag71xx_cb(struct ag71xx *ag, unsigned reg, u32 mask)
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{
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void __iomem *r;
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switch (reg) {
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case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
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case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
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r = ag->mac_base + reg;
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__raw_writel(__raw_readl(r) & ~mask, r);
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ag71xx_check_reg_offset(ag, reg);
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/* flush write */
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(void) __raw_readl(r);
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break;
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default:
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BUG();
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}
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r = ag->mac_base + reg;
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__raw_writel(__raw_readl(r) & ~mask, r);
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/* flush write */
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(void) __raw_readl(r);
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}
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static inline void ag71xx_int_enable(struct ag71xx *ag, u32 ints)
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