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Preserve fw_arg0-3 to allow runtime bootloader detection (Gabor Juhos)
SVN-Revision: 6711
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6c9b120593
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@ -30,6 +30,9 @@
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* 24-Apr-2005 Oleg I. Vdovikin
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* reordered functions using lds script, removed forward decl
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*
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* 24-Mar-2007 Gabor Juhos
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* pass original values of the a0,a1,a2,a3 registers to the kernel
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*
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*/
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#include "LzmaDecode.h"
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@ -93,6 +96,9 @@ extern unsigned char workspace[];
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unsigned int offset;
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unsigned char *data;
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typedef void (*kernel_entry)(unsigned long reg_a0, unsigned long reg_a1,
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unsigned long reg_a2, unsigned long reg_a3);
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/* flash access should be aligned, so wrapper is used */
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/* read byte from the flash, all accesses are 32-bit aligned */
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static int read_byte(void *object, unsigned char **buffer, UInt32 *bufferSize)
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@ -119,7 +125,9 @@ static __inline__ unsigned char get_byte(void)
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}
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/* should be the first function */
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void entry(unsigned long icache_size, unsigned long icache_lsize,
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void entry(unsigned long reg_a0, unsigned long reg_a1,
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unsigned long reg_a2, unsigned long reg_a3,
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unsigned long icache_size, unsigned long icache_lsize,
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unsigned long dcache_size, unsigned long dcache_lsize)
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{
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unsigned int i; /* temp value */
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@ -173,7 +181,7 @@ void entry(unsigned long icache_size, unsigned long icache_lsize,
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/* Jump to load address */
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uart_write_str("ok\r\n");
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((void (*)(void)) LOADADDR)();
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((kernel_entry) LOADADDR)(reg_a0, reg_a1, reg_a2, reg_a3);
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}
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uart_write_str("failed\r\n");
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while (1 );
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@ -1,3 +1,6 @@
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/* Copyright 2007 Gabor Juhos */
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/* keep original values of the a0,a1,a2,a3 registers */
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/* cache manipulation adapted from Broadcom code */
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/* Copyright 2005 Oleg I. Vdovikin (oleg@cs.msu.su) */
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/* cache manipulation adapted from Broadcom code */
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/* idea taken from original bunzip2 decompressor code */
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@ -40,18 +43,17 @@
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.set noreorder
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/* Copy decompressor code to the right place */
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li t2, BZ_TEXT_START
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add a0, t2, 0
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la a1, code_start
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la a2, code_stop
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li t0, BZ_TEXT_START
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la t1, code_start
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la t2, code_stop
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$L1:
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lw t0, 0(a1)
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sw t0, 0(a0)
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add a1, 4
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add a0, 4
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blt a1, a2, $L1
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nop
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lw t3, 0(t1)
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sw t3, 0(t0)
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add t1, 4
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blt t1, t2, $L1
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add t0, 4
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/* At this point we need to invalidate dcache and */
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/* icache before jumping to new code */
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@ -145,11 +147,20 @@ nodc:
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addu t0,s3
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noic:
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move a0,s3 /* icache line size */
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move a1,s4 /* icache size */
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move a2,s1 /* dcache line size */
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jal t2
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move a3,s2 /* dcache size */
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li t0, BZ_TEXT_START
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addiu sp, -32 /* reserve stack for parameters */
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#if 0
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sw a0, 0(sp)
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sw a1, 4(sp)
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sw a2, 8(sp)
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sw a3, 12(sp)
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#endif
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sw s3, 16(sp) /* icache line size */
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sw s4, 20(sp) /* icache size */
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sw s1, 24(sp) /* dcache line size */
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jr t0
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sw s2, 28(sp) /* dcache size */
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.set reorder
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END(startup)
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