mirror of
https://git.openwrt.org/openwrt/openwrt.git
synced 2024-10-18 21:48:23 +02:00
uboot-rockchip: add Orange Pi R1 Plus LTS support
Add support for the Xunlong Orange Pi R1 Plus LTS. Manually generated of-platdata files to avoid swig dependency. Tested-by: Volkan Yetik <no3iverson@gmail.com> Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
This commit is contained in:
Tianling Shen
Hauke Mehrtens
parent
ab641efe69
commit
37fed89166
@ -52,6 +52,13 @@ define U-Boot/orangepi-r1-plus-rk3328
|
||||
xunlong_orangepi-r1-plus
|
||||
endef
|
||||
|
||||
define U-Boot/orangepi-r1-plus-lts-rk3328
|
||||
$(U-Boot/rk3328/Default)
|
||||
NAME:=Orange Pi R1 Plus LTS
|
||||
BUILD_DEVICES:= \
|
||||
xunlong_orangepi-r1-plus-lts
|
||||
endef
|
||||
|
||||
define U-Boot/roc-cc-rk3328
|
||||
$(U-Boot/rk3328/Default)
|
||||
NAME:=ROC-RK3328-CC
|
||||
@ -95,6 +102,7 @@ UBOOT_TARGETS := \
|
||||
nanopi-r2c-rk3328 \
|
||||
nanopi-r2s-rk3328 \
|
||||
orangepi-r1-plus-rk3328 \
|
||||
orangepi-r1-plus-lts-rk3328 \
|
||||
roc-cc-rk3328
|
||||
|
||||
UBOOT_CONFIGURE_VARS += USE_PRIVATE_LIBGCC=yes
|
||||
|
||||
242
package/boot/uboot-rockchip/patches/104-rockchip-rk3328-Add-support-for-Orange-Pi-R1-Plus-LT.patch
Normal file
242
package/boot/uboot-rockchip/patches/104-rockchip-rk3328-Add-support-for-Orange-Pi-R1-Plus-LT.patch
Normal file
@ -0,0 +1,242 @@
|
||||
From 7a9326a96098bc63d2b60538f657c3a533415276 Mon Sep 17 00:00:00 2001
|
||||
From: Tianling Shen <cnsztl@gmail.com>
|
||||
Date: Sat, 20 May 2023 18:52:14 +0800
|
||||
Subject: [PATCH] rockchip: rk3328: Add support for Orange Pi R1 Plus LTS
|
||||
|
||||
The OrangePi R1 Plus LTS is a minor variant of OrangePi R1 Plus with
|
||||
the on-board NIC chip changed from rtl8211e to yt8531c, and RAM type
|
||||
changed from DDR4 to LPDDR3.
|
||||
|
||||
The device tree is taken from kernel v6.4-rc1.
|
||||
|
||||
Signed-off-by: Tianling Shen <cnsztl@gmail.com>
|
||||
|
||||
---
|
||||
arch/arm/dts/Makefile | 1 +
|
||||
.../rk3328-orangepi-r1-plus-lts-u-boot.dtsi | 46 +++++++
|
||||
arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts | 40 ++++++
|
||||
board/rockchip/evb_rk3328/MAINTAINERS | 6 +
|
||||
configs/orangepi-r1-plus-lts-rk3328_defconfig | 114 ++++++++++++++++++
|
||||
5 files changed, 207 insertions(+)
|
||||
create mode 100644 arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
|
||||
create mode 100644 arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts
|
||||
create mode 100644 configs/orangepi-r1-plus-lts-rk3328_defconfig
|
||||
|
||||
--- a/arch/arm/dts/Makefile
|
||||
+++ b/arch/arm/dts/Makefile
|
||||
@@ -111,6 +111,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3328) += \
|
||||
rk3328-nanopi-r2c.dtb \
|
||||
rk3328-nanopi-r2s.dtb \
|
||||
rk3328-orangepi-r1-plus.dtb \
|
||||
+ rk3328-orangepi-r1-plus-lts.dtb \
|
||||
rk3328-roc-cc.dtb \
|
||||
rk3328-rock64.dtb \
|
||||
rk3328-rock-pi-e.dtb
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
|
||||
@@ -0,0 +1,46 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
+/*
|
||||
+ * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd
|
||||
+ * (C) Copyright 2020 David Bauer
|
||||
+ */
|
||||
+
|
||||
+#include "rk3328-u-boot.dtsi"
|
||||
+#include "rk3328-sdram-lpddr3-666.dtsi"
|
||||
+/ {
|
||||
+ chosen {
|
||||
+ u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&gpio0 {
|
||||
+ u-boot,dm-spl;
|
||||
+};
|
||||
+
|
||||
+&pinctrl {
|
||||
+ u-boot,dm-spl;
|
||||
+};
|
||||
+
|
||||
+&sdmmc0m1_gpio {
|
||||
+ u-boot,dm-spl;
|
||||
+};
|
||||
+
|
||||
+&pcfg_pull_up_4ma {
|
||||
+ u-boot,dm-spl;
|
||||
+};
|
||||
+
|
||||
+/* Need this and all the pinctrl/gpio stuff above to set pinmux */
|
||||
+&vcc_sd {
|
||||
+ u-boot,dm-spl;
|
||||
+};
|
||||
+
|
||||
+&gmac2io {
|
||||
+ snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
|
||||
+ snps,reset-active-low;
|
||||
+ snps,reset-delays-us = <0 10000 50000>;
|
||||
+};
|
||||
+
|
||||
+&spi0 {
|
||||
+ spi_flash: spiflash@0 {
|
||||
+ u-boot,dm-pre-reloc;
|
||||
+ };
|
||||
+};
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts
|
||||
@@ -0,0 +1,40 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
+/*
|
||||
+ * Copyright (c) 2016 Xunlong Software. Co., Ltd.
|
||||
+ * (http://www.orangepi.org)
|
||||
+ *
|
||||
+ * Copyright (c) 2021-2023 Tianling Shen <cnsztl@gmail.com>
|
||||
+ */
|
||||
+
|
||||
+/dts-v1/;
|
||||
+#include "rk3328-orangepi-r1-plus.dts"
|
||||
+
|
||||
+/ {
|
||||
+ model = "Xunlong Orange Pi R1 Plus LTS";
|
||||
+ compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328";
|
||||
+};
|
||||
+
|
||||
+&gmac2io {
|
||||
+ phy-handle = <&yt8531c>;
|
||||
+ tx_delay = <0x19>;
|
||||
+ rx_delay = <0x05>;
|
||||
+
|
||||
+ mdio {
|
||||
+ /delete-node/ ethernet-phy@1;
|
||||
+
|
||||
+ yt8531c: ethernet-phy@0 {
|
||||
+ compatible = "ethernet-phy-ieee802.3-c22";
|
||||
+ reg = <0>;
|
||||
+
|
||||
+ motorcomm,clk-out-frequency-hz = <125000000>;
|
||||
+ motorcomm,keep-pll-enabled;
|
||||
+ motorcomm,auto-sleep-disabled;
|
||||
+
|
||||
+ pinctrl-0 = <ð_phy_reset_pin>;
|
||||
+ pinctrl-names = "default";
|
||||
+ reset-assert-us = <15000>;
|
||||
+ reset-deassert-us = <50000>;
|
||||
+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
--- a/board/rockchip/evb_rk3328/MAINTAINERS
|
||||
+++ b/board/rockchip/evb_rk3328/MAINTAINERS
|
||||
@@ -24,6 +24,12 @@ S: Maintained
|
||||
F: configs/orangepi-r1-plus-rk3328_defconfig
|
||||
F: arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
|
||||
|
||||
+ORANGEPI-R1-PLUS-LTS-RK3328
|
||||
+M: Tianling Shen <cnsztl@gmail.com>
|
||||
+S: Maintained
|
||||
+F: configs/orangepi-r1-plus-lts-rk3328_defconfig
|
||||
+F: arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
|
||||
+
|
||||
ROC-RK3328-CC
|
||||
M: Loic Devulder <ldevulder@suse.com>
|
||||
M: Chen-Yu Tsai <wens@csie.org>
|
||||
--- /dev/null
|
||||
+++ b/configs/orangepi-r1-plus-lts-rk3328_defconfig
|
||||
@@ -0,0 +1,98 @@
|
||||
+CONFIG_ARM=y
|
||||
+CONFIG_ARCH_ROCKCHIP=y
|
||||
+CONFIG_SYS_TEXT_BASE=0x00200000
|
||||
+CONFIG_SPL_GPIO_SUPPORT=y
|
||||
+CONFIG_ENV_OFFSET=0x3F8000
|
||||
+CONFIG_ROCKCHIP_RK3328=y
|
||||
+CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
|
||||
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
|
||||
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
|
||||
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
|
||||
+CONFIG_SPL_STACK_R_ADDR=0x600000
|
||||
+CONFIG_NR_DRAM_BANKS=1
|
||||
+CONFIG_DEBUG_UART_BASE=0xFF130000
|
||||
+CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
+CONFIG_SYSINFO=y
|
||||
+CONFIG_DEBUG_UART=y
|
||||
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
|
||||
+# CONFIG_ANDROID_BOOT_IMAGE is not set
|
||||
+CONFIG_FIT=y
|
||||
+CONFIG_FIT_VERBOSE=y
|
||||
+CONFIG_SPL_LOAD_FIT=y
|
||||
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus-lts.dtb"
|
||||
+CONFIG_MISC_INIT_R=y
|
||||
+# CONFIG_DISPLAY_CPUINFO is not set
|
||||
+CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
|
||||
+CONFIG_SPL_STACK_R=y
|
||||
+CONFIG_SPL_I2C_SUPPORT=y
|
||||
+CONFIG_SPL_POWER_SUPPORT=y
|
||||
+CONFIG_SPL_ATF=y
|
||||
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
|
||||
+CONFIG_CMD_BOOTZ=y
|
||||
+CONFIG_CMD_GPT=y
|
||||
+CONFIG_CMD_MMC=y
|
||||
+CONFIG_CMD_USB=y
|
||||
+# CONFIG_CMD_SETEXPR is not set
|
||||
+CONFIG_CMD_TIME=y
|
||||
+CONFIG_SPL_OF_CONTROL=y
|
||||
+CONFIG_TPL_OF_CONTROL=y
|
||||
+CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus-lts"
|
||||
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
+CONFIG_TPL_OF_PLATDATA=y
|
||||
+CONFIG_ENV_IS_IN_MMC=y
|
||||
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
+CONFIG_NET_RANDOM_ETHADDR=y
|
||||
+CONFIG_TPL_DM=y
|
||||
+CONFIG_REGMAP=y
|
||||
+CONFIG_SPL_REGMAP=y
|
||||
+CONFIG_TPL_REGMAP=y
|
||||
+CONFIG_SYSCON=y
|
||||
+CONFIG_SPL_SYSCON=y
|
||||
+CONFIG_TPL_SYSCON=y
|
||||
+CONFIG_CLK=y
|
||||
+CONFIG_SPL_CLK=y
|
||||
+CONFIG_FASTBOOT_BUF_ADDR=0x800800
|
||||
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
|
||||
+CONFIG_ROCKCHIP_GPIO=y
|
||||
+CONFIG_SYS_I2C_ROCKCHIP=y
|
||||
+CONFIG_MMC_DW=y
|
||||
+CONFIG_MMC_DW_ROCKCHIP=y
|
||||
+CONFIG_SF_DEFAULT_SPEED=20000000
|
||||
+CONFIG_DM_ETH=y
|
||||
+CONFIG_ETH_DESIGNWARE=y
|
||||
+CONFIG_GMAC_ROCKCHIP=y
|
||||
+CONFIG_PINCTRL=y
|
||||
+CONFIG_SPL_PINCTRL=y
|
||||
+CONFIG_DM_PMIC=y
|
||||
+CONFIG_PMIC_RK8XX=y
|
||||
+CONFIG_SPL_DM_REGULATOR=y
|
||||
+CONFIG_REGULATOR_PWM=y
|
||||
+CONFIG_DM_REGULATOR_FIXED=y
|
||||
+CONFIG_SPL_DM_REGULATOR_FIXED=y
|
||||
+CONFIG_REGULATOR_RK8XX=y
|
||||
+CONFIG_PWM_ROCKCHIP=y
|
||||
+CONFIG_RAM=y
|
||||
+CONFIG_SPL_RAM=y
|
||||
+CONFIG_TPL_RAM=y
|
||||
+CONFIG_DM_RESET=y
|
||||
+CONFIG_BAUDRATE=1500000
|
||||
+CONFIG_DEBUG_UART_SHIFT=2
|
||||
+CONFIG_SYSRESET=y
|
||||
+# CONFIG_TPL_SYSRESET is not set
|
||||
+CONFIG_USB=y
|
||||
+CONFIG_USB_XHCI_HCD=y
|
||||
+CONFIG_USB_XHCI_DWC3=y
|
||||
+CONFIG_USB_EHCI_HCD=y
|
||||
+CONFIG_USB_EHCI_GENERIC=y
|
||||
+CONFIG_USB_OHCI_HCD=y
|
||||
+CONFIG_USB_OHCI_GENERIC=y
|
||||
+CONFIG_USB_DWC2=y
|
||||
+CONFIG_USB_DWC3=y
|
||||
+# CONFIG_USB_DWC3_GADGET is not set
|
||||
+CONFIG_USB_GADGET=y
|
||||
+CONFIG_USB_GADGET_DWC2_OTG=y
|
||||
+CONFIG_SPL_TINY_MEMSET=y
|
||||
+CONFIG_TPL_TINY_MEMSET=y
|
||||
+CONFIG_ERRNO_STR=y
|
||||
@ -0,0 +1,24 @@
|
||||
/*
|
||||
* DO NOT MODIFY
|
||||
*
|
||||
* Declares externs for all device/uclass instances.
|
||||
* This was generated by dtoc from a .dtb (device tree binary) file.
|
||||
*/
|
||||
|
||||
#include <dm/device-internal.h>
|
||||
#include <dm/uclass-internal.h>
|
||||
|
||||
/* driver declarations - these allow DM_DRIVER_GET() to be used */
|
||||
extern U_BOOT_DRIVER(rockchip_rk3328_cru);
|
||||
extern U_BOOT_DRIVER(rockchip_rk3328_dmc);
|
||||
extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc);
|
||||
extern U_BOOT_DRIVER(ns16550_serial);
|
||||
extern U_BOOT_DRIVER(rockchip_rk3328_spi);
|
||||
extern U_BOOT_DRIVER(rockchip_rk3328_grf);
|
||||
|
||||
/* uclass driver declarations - needed for DM_UCLASS_DRIVER_REF() */
|
||||
extern UCLASS_DRIVER(clk);
|
||||
extern UCLASS_DRIVER(mmc);
|
||||
extern UCLASS_DRIVER(ram);
|
||||
extern UCLASS_DRIVER(serial);
|
||||
extern UCLASS_DRIVER(syscon);
|
||||
@ -0,0 +1,170 @@
|
||||
/*
|
||||
* DO NOT MODIFY
|
||||
*
|
||||
* Declares the U_BOOT_DRIVER() records and platform data.
|
||||
* This was generated by dtoc from a .dtb (device tree binary) file.
|
||||
*/
|
||||
|
||||
/* Allow use of U_BOOT_DRVINFO() in this file */
|
||||
#define DT_PLAT_C
|
||||
|
||||
#include <common.h>
|
||||
#include <dm.h>
|
||||
#include <dt-structs.h>
|
||||
|
||||
/*
|
||||
* driver_info declarations, ordered by 'struct driver_info' linker_list idx:
|
||||
*
|
||||
* idx driver_info driver
|
||||
* --- -------------------- --------------------
|
||||
* 0: clock_controller_at_ff440000 rockchip_rk3328_cru
|
||||
* 1: dmc rockchip_rk3328_dmc
|
||||
* 2: mmc_at_ff500000 rockchip_rk3288_dw_mshc
|
||||
* 3: serial_at_ff130000 ns16550_serial
|
||||
* 4: spi_at_ff190000 rockchip_rk3328_spi
|
||||
* 5: syscon_at_ff100000 rockchip_rk3328_grf
|
||||
* --- -------------------- --------------------
|
||||
*/
|
||||
|
||||
/*
|
||||
* Node /clock-controller@ff440000 index 0
|
||||
* driver rockchip_rk3328_cru parent None
|
||||
*/
|
||||
static struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = {
|
||||
.reg = {0xff440000, 0x1000},
|
||||
.rockchip_grf = 0x38,
|
||||
};
|
||||
U_BOOT_DRVINFO(clock_controller_at_ff440000) = {
|
||||
.name = "rockchip_rk3328_cru",
|
||||
.plat = &dtv_clock_controller_at_ff440000,
|
||||
.plat_size = sizeof(dtv_clock_controller_at_ff440000),
|
||||
.parent_idx = -1,
|
||||
};
|
||||
|
||||
/*
|
||||
* Node /dmc index 1
|
||||
* driver rockchip_rk3328_dmc parent None
|
||||
*/
|
||||
static struct dtd_rockchip_rk3328_dmc dtv_dmc = {
|
||||
.reg = {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000,
|
||||
0xff720000, 0x1000, 0xff798000, 0x1000},
|
||||
.rockchip_sdram_params = {0x1, 0xc, 0x3, 0x1, 0x0, 0x0, 0x10, 0x10,
|
||||
0x10, 0x10, 0x0, 0x8c48a18a, 0x0, 0x21, 0x482, 0x15,
|
||||
0x21a, 0xff, 0x14d, 0x6, 0x1, 0x0, 0x0, 0x0,
|
||||
0x43041008, 0x64, 0x140023, 0xd0, 0x220002, 0xd4, 0x10000, 0xd8,
|
||||
0x703, 0xdc, 0x830004, 0xe0, 0x10000, 0xe4, 0x70003, 0xf4,
|
||||
0xf011f, 0x100, 0x6090b07, 0x104, 0x2020b, 0x108, 0x2030506, 0x10c,
|
||||
0x505000, 0x110, 0x3020204, 0x114, 0x1010303, 0x118, 0x2020003, 0x120,
|
||||
0x303, 0x138, 0x25, 0x180, 0x3c000f, 0x184, 0x900000, 0x190,
|
||||
0x7020000, 0x198, 0x5001100, 0x1a0, 0xc0400003, 0x240, 0x900090c, 0x244,
|
||||
0x101, 0x250, 0xf00, 0x490, 0x1, 0xffffffff, 0xffffffff, 0xffffffff,
|
||||
0xffffffff, 0xffffffff, 0xffffffff, 0x4, 0xb, 0x28, 0x6, 0x2c,
|
||||
0x0, 0x30, 0x3, 0xffffffff, 0xffffffff, 0x77, 0x88, 0x79,
|
||||
0x79, 0x87, 0x97, 0x87, 0x78, 0x77, 0x78, 0x87,
|
||||
0x88, 0x87, 0x87, 0x77, 0x78, 0x78, 0x78, 0x78,
|
||||
0x78, 0x78, 0x78, 0x78, 0x78, 0x69, 0x9, 0x77,
|
||||
0x78, 0x77, 0x78, 0x77, 0x78, 0x77, 0x78, 0x77,
|
||||
0x79, 0x9, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
|
||||
0x78, 0x78, 0x78, 0x69, 0x9, 0x77, 0x78, 0x77,
|
||||
0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x9,
|
||||
0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
|
||||
0x78, 0x69, 0x9, 0x77, 0x78, 0x77, 0x78, 0x77,
|
||||
0x78, 0x77, 0x78, 0x77, 0x79, 0x9, 0x78, 0x78,
|
||||
0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x69,
|
||||
0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77,
|
||||
0x77, 0x77, 0x79, 0x9},
|
||||
};
|
||||
U_BOOT_DRVINFO(dmc) = {
|
||||
.name = "rockchip_rk3328_dmc",
|
||||
.plat = &dtv_dmc,
|
||||
.plat_size = sizeof(dtv_dmc),
|
||||
.parent_idx = -1,
|
||||
};
|
||||
|
||||
/*
|
||||
* Node /mmc@ff500000 index 2
|
||||
* driver rockchip_rk3288_dw_mshc parent None
|
||||
*/
|
||||
static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = {
|
||||
.bus_width = 0x4,
|
||||
.cap_sd_highspeed = true,
|
||||
.clocks = {
|
||||
{0, {317}},
|
||||
{0, {33}},
|
||||
{0, {74}},
|
||||
{0, {78}},},
|
||||
.disable_wp = true,
|
||||
.fifo_depth = 0x100,
|
||||
.interrupts = {0x0, 0xc, 0x4},
|
||||
.max_frequency = 0x8f0d180,
|
||||
.pinctrl_0 = {0x45, 0x46, 0x47, 0x48},
|
||||
.pinctrl_names = "default",
|
||||
.reg = {0xff500000, 0x4000},
|
||||
.u_boot_spl_fifo_mode = true,
|
||||
.vmmc_supply = 0x49,
|
||||
};
|
||||
U_BOOT_DRVINFO(mmc_at_ff500000) = {
|
||||
.name = "rockchip_rk3288_dw_mshc",
|
||||
.plat = &dtv_mmc_at_ff500000,
|
||||
.plat_size = sizeof(dtv_mmc_at_ff500000),
|
||||
.parent_idx = -1,
|
||||
};
|
||||
|
||||
/*
|
||||
* Node /serial@ff130000 index 3
|
||||
* driver ns16550_serial parent None
|
||||
*/
|
||||
static struct dtd_ns16550_serial dtv_serial_at_ff130000 = {
|
||||
.clock_frequency = 0x16e3600,
|
||||
.clocks = {
|
||||
{0, {40}},
|
||||
{0, {212}},},
|
||||
.dma_names = {"tx", "rx"},
|
||||
.dmas = {0x10, 0x6, 0x10, 0x7},
|
||||
.interrupts = {0x0, 0x39, 0x4},
|
||||
.pinctrl_0 = 0x24,
|
||||
.pinctrl_names = "default",
|
||||
.reg = {0xff130000, 0x100},
|
||||
.reg_io_width = 0x4,
|
||||
.reg_shift = 0x2,
|
||||
};
|
||||
U_BOOT_DRVINFO(serial_at_ff130000) = {
|
||||
.name = "ns16550_serial",
|
||||
.plat = &dtv_serial_at_ff130000,
|
||||
.plat_size = sizeof(dtv_serial_at_ff130000),
|
||||
.parent_idx = -1,
|
||||
};
|
||||
|
||||
/* Node /spi@ff190000 index 4 */
|
||||
static struct dtd_rockchip_rk3328_spi dtv_spi_at_ff190000 = {
|
||||
.clocks = {
|
||||
{0, {32}},
|
||||
{0, {209}},},
|
||||
.dma_names = {"tx", "rx"},
|
||||
.dmas = {0x10, 0x8, 0x10, 0x9},
|
||||
.interrupts = {0x0, 0x31, 0x4},
|
||||
.pinctrl_0 = {0x2c, 0x2d, 0x2e, 0x2f},
|
||||
.pinctrl_names = "default",
|
||||
.reg = {0xff190000, 0x1000},
|
||||
};
|
||||
U_BOOT_DRVINFO(spi_at_ff190000) = {
|
||||
.name = "rockchip_rk3328_spi",
|
||||
.plat = &dtv_spi_at_ff190000,
|
||||
.plat_size = sizeof(dtv_spi_at_ff190000),
|
||||
.parent_idx = -1,
|
||||
};
|
||||
|
||||
/*
|
||||
* Node /syscon@ff100000 index 5
|
||||
* driver rockchip_rk3328_grf parent None
|
||||
*/
|
||||
static struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = {
|
||||
.reg = {0xff100000, 0x1000},
|
||||
};
|
||||
U_BOOT_DRVINFO(syscon_at_ff100000) = {
|
||||
.name = "rockchip_rk3328_grf",
|
||||
.plat = &dtv_syscon_at_ff100000,
|
||||
.plat_size = sizeof(dtv_syscon_at_ff100000),
|
||||
.parent_idx = -1,
|
||||
};
|
||||
|
||||
55
package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-lts-rk3328/dt-structs-gen.h
Normal file
55
package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-lts-rk3328/dt-structs-gen.h
Normal file
@ -0,0 +1,55 @@
|
||||
/*
|
||||
* DO NOT MODIFY
|
||||
*
|
||||
* Defines the structs used to hold devicetree data.
|
||||
* This was generated by dtoc from a .dtb (device tree binary) file.
|
||||
*/
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <linux/libfdt.h>
|
||||
struct dtd_ns16550_serial {
|
||||
fdt32_t clock_frequency;
|
||||
struct phandle_1_arg clocks[2];
|
||||
const char * dma_names[2];
|
||||
fdt32_t dmas[4];
|
||||
fdt32_t interrupts[3];
|
||||
fdt32_t pinctrl_0;
|
||||
const char * pinctrl_names;
|
||||
fdt64_t reg[2];
|
||||
fdt32_t reg_io_width;
|
||||
fdt32_t reg_shift;
|
||||
};
|
||||
struct dtd_rockchip_rk3288_dw_mshc {
|
||||
fdt32_t bus_width;
|
||||
bool cap_sd_highspeed;
|
||||
struct phandle_1_arg clocks[4];
|
||||
bool disable_wp;
|
||||
fdt32_t fifo_depth;
|
||||
fdt32_t interrupts[3];
|
||||
fdt32_t max_frequency;
|
||||
fdt32_t pinctrl_0[4];
|
||||
const char * pinctrl_names;
|
||||
fdt64_t reg[2];
|
||||
bool u_boot_spl_fifo_mode;
|
||||
fdt32_t vmmc_supply;
|
||||
};
|
||||
struct dtd_rockchip_rk3328_cru {
|
||||
fdt64_t reg[2];
|
||||
fdt32_t rockchip_grf;
|
||||
};
|
||||
struct dtd_rockchip_rk3328_dmc {
|
||||
fdt64_t reg[12];
|
||||
fdt32_t rockchip_sdram_params[196];
|
||||
};
|
||||
struct dtd_rockchip_rk3328_grf {
|
||||
fdt64_t reg[2];
|
||||
};
|
||||
struct dtd_rockchip_rk3328_spi {
|
||||
struct phandle_1_arg clocks[2];
|
||||
const char * dma_names[2];
|
||||
fdt32_t dmas[4];
|
||||
fdt32_t interrupts[3];
|
||||
fdt32_t pinctrl_0[4];
|
||||
const char * pinctrl_names;
|
||||
fdt64_t reg[2];
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user