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fix MISC IRQ handling on the AR7240
SVN-Revision: 17098
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cf176f82db
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@ -297,22 +297,6 @@ static void ar71xx_misc_irq_unmask(unsigned int irq)
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ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
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}
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static void ar724x_misc_irq_unmask(unsigned int irq)
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{
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irq -= AR71XX_MISC_IRQ_BASE;
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ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE,
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ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE) | (1 << irq));
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/* flush write */
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ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
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ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_STATUS,
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ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_STATUS) & ~(1 << irq));
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/* flush write */
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ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_STATUS);
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}
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static void ar71xx_misc_irq_mask(unsigned int irq)
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{
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irq -= AR71XX_MISC_IRQ_BASE;
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@ -323,11 +307,20 @@ static void ar71xx_misc_irq_mask(unsigned int irq)
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ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
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}
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static void ar724x_misc_irq_ack(unsigned int irq)
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{
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irq -= AR71XX_MISC_IRQ_BASE;
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ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_STATUS,
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ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_STATUS) & ~(1 << irq));
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/* flush write */
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ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_STATUS);
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}
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static struct irq_chip ar71xx_misc_irq_chip = {
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.name = "AR71XX MISC",
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.unmask = ar71xx_misc_irq_unmask,
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.mask = ar71xx_misc_irq_mask,
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.mask_ack = ar71xx_misc_irq_mask,
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};
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static struct irqaction ar71xx_misc_irqaction = {
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@ -343,7 +336,9 @@ static void __init ar71xx_misc_irq_init(void)
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ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_STATUS, 0);
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if (ar71xx_soc == AR71XX_SOC_AR7240)
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ar71xx_misc_irq_chip.unmask = ar724x_misc_irq_unmask;
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ar71xx_misc_irq_chip.ack = ar724x_misc_irq_ack;
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else
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ar71xx_misc_irq_chip.mask_ack = ar71xx_misc_irq_mask;
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for (i = AR71XX_MISC_IRQ_BASE;
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i < AR71XX_MISC_IRQ_BASE + AR71XX_MISC_IRQ_COUNT; i++) {
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