91 lines
1.8 KiB
C
91 lines
1.8 KiB
C
/*
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* (C) Copyright 2008
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _KWBIMAGE_H_
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#define _KWBIMAGE_H_
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#include <stdint.h>
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#define KWBIMAGE_MAX_CONFIG ((0x1dc - 0x20)/sizeof(struct reg_config))
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#define MAX_TEMPBUF_LEN 32
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/* NAND ECC Mode */
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#define IBR_HDR_ECC_DEFAULT 0x00
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#define IBR_HDR_ECC_FORCED_HAMMING 0x01
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#define IBR_HDR_ECC_FORCED_RS 0x02
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#define IBR_HDR_ECC_DISABLED 0x03
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/* Boot Type - block ID */
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#define IBR_HDR_I2C_ID 0x4D
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#define IBR_HDR_SPI_ID 0x5A
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#define IBR_HDR_NAND_ID 0x8B
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#define IBR_HDR_SATA_ID 0x78
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#define IBR_HDR_PEX_ID 0x9C
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#define IBR_HDR_UART_ID 0x69
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#define IBR_DEF_ATTRIB 0x00
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enum kwbimage_cmd {
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CMD_INVALID,
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CMD_BOOT_FROM,
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CMD_NAND_ECC_MODE,
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CMD_NAND_PAGE_SIZE,
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CMD_SATA_PIO_MODE,
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CMD_DDR_INIT_DELAY,
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CMD_DATA
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};
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enum kwbimage_cmd_types {
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CFG_INVALID = -1,
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CFG_COMMAND,
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CFG_DATA0,
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CFG_DATA1
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};
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/* typedefs */
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typedef struct bhr_t {
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uint8_t blockid; /*0 */
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uint8_t nandeccmode; /*1 */
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uint16_t nandpagesize; /*2-3 */
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uint32_t blocksize; /*4-7 */
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uint32_t rsvd1; /*8-11 */
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uint32_t srcaddr; /*12-15 */
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uint32_t destaddr; /*16-19 */
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uint32_t execaddr; /*20-23 */
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uint8_t satapiomode; /*24 */
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uint8_t rsvd3; /*25 */
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uint16_t ddrinitdelay; /*26-27 */
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uint16_t rsvd2; /*28-29 */
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uint8_t ext; /*30 */
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uint8_t checkSum; /*31 */
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} bhr_t, *pbhr_t;
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struct reg_config {
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uint32_t raddr;
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uint32_t rdata;
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};
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typedef struct extbhr_t {
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uint32_t dramregsoffs;
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uint8_t rsrvd1[0x20 - sizeof(uint32_t)];
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struct reg_config rcfg[KWBIMAGE_MAX_CONFIG];
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uint8_t rsrvd2[7];
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uint8_t checkSum;
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} extbhr_t, *pextbhr_t;
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struct kwb_header {
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bhr_t kwb_hdr;
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extbhr_t kwb_exthdr;
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};
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/*
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* functions
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*/
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void init_kwb_image_type (void);
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#endif /* _KWBIMAGE_H_ */
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