61 lines
1.0 KiB
ArmAsm
Executable File
61 lines
1.0 KiB
ArmAsm
Executable File
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#include "config.h"
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.globl _start
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_start: b reset
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ldr pc, __nop
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ldr pc, __nop
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ldr pc, __nop
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ldr pc, __nop
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ldr pc, __nop
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ldr pc, __nop
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ldr pc, __nop
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reset:
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bl cpu_init_crit
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bl clear_bss
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ldr sp, =CONFIG_STACK_BASE
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bl sbromsw_entry
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b .
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__nop:
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b __nop
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clear_bss:
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ldr r0, =__bss_start
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ldr r1, =__bss_end
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mov r2, #0x00000000 /* clear */
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clbss_l:
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str r2, [r0] /* clear loop... */
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add r0, r0, #4
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cmp r0, r1
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bne clbss_l
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mov pc, lr
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cpu_init_crit:
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@Invalidate L1 I/D
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mov r0, #0 @ set up for MCR
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mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
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mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
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mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array
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mcr p15, 0, r0, c7, c10, 4 @ DSB
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mcr p15, 0, r0, c7, c5, 4 @ ISB
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@disable MMU stuff and caches
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r0, #0x00002000 @ clear bits 13 (--V-)
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bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM)
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orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB
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@enable I-cache
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orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache
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mcr p15, 0, r0, c1, c0, 0
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mov pc, lr
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