88 lines
3.1 KiB
ArmAsm
Executable File
88 lines
3.1 KiB
ArmAsm
Executable File
/*
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**********************************************************************************************************************
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*
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* the Embedded Secure Bootloader System
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*
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*
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* Copyright(C), 2006-2014, Allwinnertech Co., Ltd.
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* All Rights Reserved
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*
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* File :
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*
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* By :
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*
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* Version : V2.00
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*
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* Date :
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*
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* Descript:
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**********************************************************************************************************************
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*/
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#include "common.h"
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#include "asm/arch/platform.h"
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/*----------------------------------------------------------------------------*/
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/* Description of SCR (Secure Configuration Register) */
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/* */
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/* | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 | */
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/* | bit6 | AW | FW | EA | FIQ | IRQ | NS | */
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/* */
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/* AW =0 the CPSR.A bit can be modified only in Secure state */
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/* =1 the CPSR.A bit can be modified in any security state */
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/* */
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/* FW =0 the CPSR.F bit can be modified only in Secure state */
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/* =1 the CPSR.F bit can be modified in any security state */
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/* */
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/* EA =0 Abort mode handles external aborts */
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/* =1 Monitor mode handles external aborts */
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/* */
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/* FIQ =0 FIQ mode entered when FIQ is taken */
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/* =1 Monitor mode entered when FIQ is taken */
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/* */
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/* IRQ =0 IRQ mode entered when IRQ is taken */
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/* =1 Monitor mode entered when IRQ is taken */
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/* */
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/* NS =0 Secure state */
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/* =1 Non-secure state */
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/* */
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/*----------------------------------------------------------------------------*/
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.globl secure_switch_unsecure
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secure_switch_unsecure:
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mrc p15, 0, r2, c1, c1, 2
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ldr r3, =(0xC00 | (0x03<<18))
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orr r2, r2, r3
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mcr p15, 0, r2, c1, c1, 2 @ʹ<><CAB9>NSACR<43><52>CP11,CP10
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mov r4, r0
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cps #0x16 @<40><>ȡCPSR
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msr spsr_cxsf, #0x13
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mrc p15, 0, r5, c1, c1, 0
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tst r5, #1
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bne __switch_out
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mov r0, #0x31 @r0 = (1<<4 | 1<<3 | 1<<0);
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mcr p15, 0, r0, c1, c1, 0
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mov r0, #0 @<40><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>branch
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mcr p15, 0, r0, c7, c5, 6
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__switch_out:
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movs pc, r4
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.globl secure_switch_other
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secure_switch_other:
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stmfd sp!, {r2, lr}
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mov r2, r0
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mov r0, r1
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blx r2
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ldmfd sp!, {r2, pc}
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