121 lines
3.9 KiB
C
121 lines
3.9 KiB
C
/*
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* (C) Copyright 2007-2013
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* Jerry Wang <wangflord@allwinnertech.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include "common.h"
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#include "asm/arch/archdef.h"
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#include "asm/arch/timer.h"
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/*
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************************************************************************************************************
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*
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* function
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*
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* name :
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*
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* parmeters :
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*
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* return :
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*
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* note :
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*
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*
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************************************************************************************************************
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*/
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void mmu_setup(u32 dram_size)
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{
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u32 mmu_base;
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//u32 *page_table = (u32 *)BOOT0_MMU_BASE_ADDRESS;
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//use dram high 16M
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u32* mmu_base_addr = (u32 *)(PLAT_SDRAM_BASE +((dram_size-16)<<20));
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u32* page_table = mmu_base_addr;
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int i;
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u32 reg;
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page_table[0] = (3 << 10) | (15 << 5) | (1 << 3) | (0 << 2) | 0x2;
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/* the front 1G of memory(treated as 4G for all) is set up as none cacheable */
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for (i = 1; i < (PLAT_SDRAM_BASE>>20); i++)
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page_table[i] = (i << 20) | (3 << 10) | (15 << 5) | (0 << 3) | 0x2;
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/* Set up as write through and buffered(not write back) for other 3GB, rw for everyone */
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for (i = (PLAT_SDRAM_BASE>>20); i < 4096; i++)
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page_table[i] = (i << 20) | (3 << 10) | (15 << 5) | (1 << 3) | (0 << 2) | 0x2;
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/* flush tlb */
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asm volatile("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
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/* Copy the page table address to cp15 */
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mmu_base = (u32)mmu_base_addr;
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mmu_base |= (1 << 0) | (1 << 1) | (2 << 3);
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asm volatile("mcr p15, 0, %0, c2, c0, 0"
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: : "r" (mmu_base) : "memory");
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asm volatile("mcr p15, 0, %0, c2, c0, 1"
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: : "r" (mmu_base) : "memory");
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/* Set the access control to all-supervisor */
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asm volatile("mcr p15, 0, %0, c3, c0, 0"
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: : "r" (0x55555555)); //modified, origin value is (~0)
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asm volatile("isb");
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/* and enable the mmu */
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asm volatile("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (reg) : : "cc");
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__usdelay(100);
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reg |= 1; //enable mmu
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asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR" : : "r" (reg) : "cc");
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asm volatile("isb");
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}
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/*
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************************************************************************************************************
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*
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* function
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*
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* name :
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*
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* parmeters :
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*
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* return :
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*
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* note :
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*
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*
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************************************************************************************************************
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*/
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void mmu_turn_off( void )
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{
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uint reg;
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/* and disable the mmu */
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asm volatile("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (reg) : : "cc");
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__usdelay(100);
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reg &= ~((7<<0)|(1<<12)); //disable mmu
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asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR" : : "r" (reg) : "cc");
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ARCHISB;
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/*
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* Invalidate all instruction caches to PoU.
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* Also flushes branch target cache.
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*/
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asm volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
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/* Invalidate entire branch predictor array */
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asm volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
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/* Full system DSB - make sure that the invalidation is complete */
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ARCHDSB;
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/* ISB - make sure the instruction stream sees it */
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ARCHISB;
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}
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