514 lines
18 KiB
C
514 lines
18 KiB
C
/*
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* drivers/arisc/arisc.c
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*
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* Copyright (c) 2012 Allwinner.
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* 2012-05-01 Written by sunny (sunny@allwinnertech.com).
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* 2012-10-01 Written by superm (superm@allwinnertech.com).
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include "arisc_i.h"
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#include <smc.h>
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#include <sunxi_board.h>
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//if all value are zero , compile will not allocate space to this global variable.
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//use them before uboot Relocation will cause error.
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struct dts_cfg dts_cfg =
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{
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.dram_para = {0x1,0x1}
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};
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struct dts_cfg_64 dts_cfg_64 =
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{
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.dram_para = {0x1,0x1}
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};
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unsigned int arisc_debug_level = 2;
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static int get_image_addr_size(phys_addr_t *image_addr, size_t *image_size)
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{
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struct spare_boot_head_t *header;
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phys_addr_t offset;
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size_t size;
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/* Obtain a reference to the image by querying the platform layer */
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header = &uboot_spare_head;
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offset = header->boot_ext[2].data[0];
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size = header->boot_ext[2].data[1];
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if(0 == offset || 0 == size)
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{
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printf("arisc image file not found\n");
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return -1;
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}
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*image_addr = (ptrdiff_t)CONFIG_SYS_TEXT_BASE + offset;
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*image_size = size;
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return 0;
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}
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int arisc_dvfs_cfg_vf_table(void)
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{
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u32 value = 0;
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int index = 0;
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int nodeoffset;
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u32 vf_table_size = 0;
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char vf_table_main_key[64];
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char vf_table_sub_key[64];
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u32 vf_table_count = 0;
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u32 vf_table_type = 0;
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nodeoffset = fdt_node_offset_by_compatible(working_fdt, -1, "allwinner,dvfs_table");
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if (IS_ERR_VALUE(nodeoffset)) {
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ARISC_ERR("get [allwinner,dvfs_table] device node error\n");
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return -EINVAL;
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}
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if (IS_ERR_VALUE(fdt_getprop_u32(working_fdt, nodeoffset, "vf_table_count", &vf_table_count))) {
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ARISC_LOG("%s: support only one vf_table\n", __func__);
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sprintf(vf_table_main_key, "%s", "allwinner,dvfs_table");
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} else {
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//vf_table_type = sunxi_get_soc_bin();
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sprintf(vf_table_main_key, "%s%d", "allwinner,vf_table", vf_table_type);
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}
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ARISC_INF("%s: vf table type [%d=%s]\n", __func__, vf_table_type, vf_table_main_key);
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nodeoffset = fdt_node_offset_by_compatible(working_fdt, -1, vf_table_main_key);
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if (IS_ERR_VALUE(nodeoffset)) {
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ARISC_ERR("get [%s] device node error\n", vf_table_main_key);
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return -EINVAL;
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}
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/* parse system config v-f table information */
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if (IS_ERR_VALUE(fdt_getprop_u32(working_fdt, nodeoffset, "lv_count", &vf_table_size))) {
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ARISC_ERR("parse system config dvfs_table size fail\n");
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return -EINVAL;
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}
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for (index = 0; index < vf_table_size; index++) {
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sprintf(vf_table_sub_key, "lv%d_freq", index + 1);
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if (!IS_ERR_VALUE(fdt_getprop_u32(working_fdt, nodeoffset, vf_table_sub_key, &value))) {
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dts_cfg.vf[index].freq = value;
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}
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ARISC_INF("%s: freq [%s-%d=%d]\n", __func__, vf_table_sub_key, index, value);
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sprintf(vf_table_sub_key, "lv%d_volt", index + 1);
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if (!IS_ERR_VALUE(fdt_getprop_u32(working_fdt, nodeoffset, vf_table_sub_key, &value))) {
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dts_cfg.vf[index].voltage = value;
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}
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ARISC_INF("%s: volt [%s-%d=%d]\n", __func__, vf_table_sub_key, index, value);
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}
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return 0;
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}
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static int sunxi_arisc_parse_cfg(void)
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{
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u32 value[4] = {0, 0, 0};
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int nodeoffset;
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/* parse arisc node */
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nodeoffset = fdt_node_offset_by_compatible(working_fdt, -1, "allwinner,sunxi-arisc");
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if (IS_ERR_VALUE(nodeoffset)) {
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ARISC_ERR("get [allwinner,sunxi-arisc] device node error\n");
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return -EINVAL;
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}
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if (IS_ERR_VALUE(fdt_getprop_u32(working_fdt, nodeoffset, "powchk_used", &dts_cfg.power.powchk_used))) {
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ARISC_ERR("parse power powchk_used fail\n");
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return -EINVAL;
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}
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ARISC_INF("powchk_used:0x%x\n", dts_cfg.power.powchk_used);
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if (IS_ERR_VALUE(fdt_getprop_u32(working_fdt, nodeoffset, "power_reg", &dts_cfg.power.power_reg))) {
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ARISC_ERR("parse power power_reg fail\n");
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return -EINVAL;
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}
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ARISC_INF("power_reg:0x%x\n", dts_cfg.power.power_reg);
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if (IS_ERR_VALUE(fdt_getprop_u32(working_fdt, nodeoffset, "system_power", &dts_cfg.power.system_power))) {
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ARISC_ERR("parse power system_power fail\n");
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return -EINVAL;
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}
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ARISC_INF("system_power:0x%x\n", dts_cfg.power.system_power);
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/* parse arisc_space node */
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nodeoffset = fdt_node_offset_by_compatible(working_fdt, -1, "allwinner,arisc_space");
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if (IS_ERR_VALUE(nodeoffset)) {
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ARISC_ERR("get [allwinner,arisc_space] device node error\n");
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return -EINVAL;
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}
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if (IS_ERR_VALUE(fdt_getprop_u32(working_fdt, nodeoffset, "space1", value))) {
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ARISC_ERR("get arisc_space space1 error\n");
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return -EINVAL;
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}
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dts_cfg.space.sram_dst = (phys_addr_t)value[0];
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dts_cfg.space.sram_offset = (phys_addr_t)value[1];
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dts_cfg.space.sram_size = (size_t)value[2];
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if (IS_ERR_VALUE(fdt_getprop_u32(working_fdt, nodeoffset, "space2", value))) {
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ARISC_ERR("get arisc_space space2 error\n");
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return -EINVAL;
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}
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dts_cfg.space.dram_dst = (phys_addr_t)value[0];
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dts_cfg.space.dram_offset = (phys_addr_t)value[1];
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dts_cfg.space.dram_size = (size_t)value[2];
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if (IS_ERR_VALUE(fdt_getprop_u32(working_fdt, nodeoffset, "space3", value))) {
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ARISC_ERR("get arisc_space space3 error\n");
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return -EINVAL;
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}
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dts_cfg.space.para_dst = (phys_addr_t)value[0];
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dts_cfg.space.para_offset = (phys_addr_t)value[1];
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dts_cfg.space.para_size = (size_t)value[2];
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if (IS_ERR_VALUE(fdt_getprop_u32(working_fdt, nodeoffset, "space4", value))) {
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ARISC_ERR("get arisc_space space4 error\n");
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return -EINVAL;
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}
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dts_cfg.space.msgpool_dst = (phys_addr_t)value[0];
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dts_cfg.space.msgpool_offset = (phys_addr_t)value[1];
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dts_cfg.space.msgpool_size = (size_t)value[2];
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ARISC_INF("arisc_space space1 sram_dst:0x%p, sram_offset:0x%p, sram_size:0x%zx, \n",
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(void *)dts_cfg.space.sram_dst, (void *)dts_cfg.space.sram_offset, dts_cfg.space.sram_size);
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ARISC_INF("arisc_space space2 dram_dst:0x%p, dram_offset:0x%p, dram_size:0x%zx, \n",
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(void *)dts_cfg.space.dram_dst, (void *)dts_cfg.space.dram_offset, dts_cfg.space.dram_size);
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ARISC_INF("arisc_space space3 para_dst:0x%p, para_offset:0x%p, para_size:0x%zx, \n",
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(void *)dts_cfg.space.para_dst, (void *)dts_cfg.space.para_offset, dts_cfg.space.para_size);
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ARISC_INF("arisc_space space4 msgpool_dst:0x%p, msgpool_offset:0x%p, msgpool_size:0x%zx, \n",
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(void *)dts_cfg.space.msgpool_dst, (void *)dts_cfg.space.msgpool_offset, dts_cfg.space.msgpool_size);
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/* parse standby_space node */
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nodeoffset = fdt_node_offset_by_compatible(working_fdt, -1, "allwinner,standby_space");
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if (IS_ERR_VALUE(nodeoffset)) {
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ARISC_ERR("get [allwinner,standby_space] device node error\n");
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return -EINVAL;
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}
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if (IS_ERR_VALUE(fdt_getprop_u32(working_fdt, nodeoffset, "space1", value))) {
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ARISC_ERR("get standby_space space1 error\n");
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return -EINVAL;
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}
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dts_cfg.space.standby_dst = (phys_addr_t)value[0];
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dts_cfg.space.standby_offset = (phys_addr_t)value[1];
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dts_cfg.space.standby_size = (size_t)value[2];
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ARISC_INF("standby_space space1 standby_dst:0x%p, standby_offset:0x%p, standby_size:0x%zx, \n",
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(void *)dts_cfg.space.standby_dst, (void *)dts_cfg.space.standby_offset, dts_cfg.space.standby_size);
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/* parse image para */
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get_image_addr_size(&dts_cfg.image.base, &dts_cfg.image.size);
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ARISC_INF("image base:0x%p, image size:0x%zx\n", (void *)dts_cfg.image.base, dts_cfg.image.size);
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/* parse dram node */
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memcpy((void *)&dts_cfg.dram_para, (void *)(uboot_spare_head.boot_data.dram_para), sizeof(dts_cfg.dram_para));
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/* parse prcm node */
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nodeoffset = fdt_node_offset_by_compatible(working_fdt, -1, "allwinner,prcm");
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if (IS_ERR_VALUE(nodeoffset)) {
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ARISC_ERR("get [allwinner,prcm] device node error\n");
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return -EINVAL;
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}
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if (IS_ERR_VALUE(fdt_getprop_u32(working_fdt, nodeoffset, "reg", value))) {
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ARISC_ERR("get prcm reg error\n");
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return -EINVAL;
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}
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dts_cfg.prcm.base = (phys_addr_t)value[1];
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dts_cfg.prcm.size = (size_t)value[3];
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ARISC_INF("prcm base:0x%p, size:0x%zx\n",
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(void *)dts_cfg.prcm.base, dts_cfg.prcm.size);
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/* parse cpuscfg node */
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nodeoffset = fdt_node_offset_by_compatible(working_fdt, -1, "allwinner,cpuscfg");
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if (IS_ERR_VALUE(nodeoffset)) {
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ARISC_ERR("get [allwinner,cpuscfg] device node error\n");
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return -EINVAL;
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}
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if (IS_ERR_VALUE(fdt_getprop_u32(working_fdt, nodeoffset, "reg", value))) {
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ARISC_ERR("get cpuscfg reg error\n");
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return -EINVAL;
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}
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dts_cfg.cpuscfg.base = (phys_addr_t)value[1];
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dts_cfg.cpuscfg.size = (size_t)value[3];
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ARISC_INF("cpuscfg base:0x%p, size:0x%zx\n",
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(void *)dts_cfg.cpuscfg.base, dts_cfg.cpuscfg.size);
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/* parse msgbox node */
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nodeoffset = fdt_node_offset_by_compatible(working_fdt, -1, "allwinner,msgbox");
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if (IS_ERR_VALUE(nodeoffset)) {
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ARISC_ERR("get [allwinner,msgbox] device node error\n");
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return -EINVAL;
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}
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if (IS_ERR_VALUE(fdt_getprop_u32(working_fdt, nodeoffset, "reg", value))) {
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ARISC_ERR("get msgbox reg error\n");
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return -EINVAL;
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}
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dts_cfg.msgbox.base = (phys_addr_t)value[1];
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dts_cfg.msgbox.size = (size_t)value[3];
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dts_cfg.msgbox.status = fdtdec_get_is_enabled(working_fdt, nodeoffset);
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ARISC_INF("msgbox base:0x%p, size:0x%zx, status:%u\n",
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(void *)dts_cfg.msgbox.base, dts_cfg.msgbox.size, dts_cfg.msgbox.status);
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/* parse hwspinlock node */
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nodeoffset = fdt_node_offset_by_compatible(working_fdt, -1, "allwinner,sunxi-hwspinlock");
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if (IS_ERR_VALUE(nodeoffset)) {
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ARISC_ERR("get [allwinner,sunxi-hwspinlock] device node error\n");
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return -EINVAL;
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}
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if (IS_ERR_VALUE(fdt_getprop_u32(working_fdt, nodeoffset, "reg", value))) {
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ARISC_ERR("get sunxi-hwspinlock reg error\n");
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return -EINVAL;
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}
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dts_cfg.hwspinlock.base = (phys_addr_t)value[1];
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dts_cfg.hwspinlock.size = (size_t)value[3];
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dts_cfg.hwspinlock.status = fdtdec_get_is_enabled(working_fdt, nodeoffset);
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ARISC_INF("hwspinlock base:0x%p, size:0x%zx, status:%u\n",
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(void *)dts_cfg.hwspinlock.base, dts_cfg.hwspinlock.size, dts_cfg.hwspinlock.status);
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/* parse s_uart node */
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nodeoffset = fdt_node_offset_by_compatible(working_fdt, -1, "allwinner,s_uart");
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if (IS_ERR_VALUE(nodeoffset)) {
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ARISC_ERR("get [allwinner,s_uart] device node error\n");
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return -EINVAL;
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}
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if (IS_ERR_VALUE(fdt_getprop_u32(working_fdt, nodeoffset, "reg", value))) {
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ARISC_ERR("get s_uart reg error\n");
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return -EINVAL;
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}
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dts_cfg.s_uart.base = (phys_addr_t)value[1];
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dts_cfg.s_uart.size = (size_t)value[3];
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ARISC_INF("s_uart base:0x%p, size:0x%zx\n",
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(void *)dts_cfg.s_uart.base, dts_cfg.s_uart.size);
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dts_cfg.s_uart.status = fdtdec_get_is_enabled(working_fdt, nodeoffset);
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ARISC_INF("s_uart base:0x%p, size:0x%zx, status:%u\n",
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(void *)dts_cfg.s_uart.base, dts_cfg.s_uart.size, dts_cfg.s_uart.status);
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/* parse s_rsb node */
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nodeoffset = fdt_node_offset_by_compatible(working_fdt, -1, "allwinner,s_rsb");
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if (IS_ERR_VALUE(nodeoffset)) {
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ARISC_ERR("get [allwinner,s_rsb] device node error\n");
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return -EINVAL;
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}
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if (IS_ERR_VALUE(fdt_getprop_u32(working_fdt, nodeoffset, "reg", value))) {
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ARISC_ERR("get s_rsb reg error\n");
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return -EINVAL;
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}
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dts_cfg.s_rsb.base = (phys_addr_t)value[1];
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dts_cfg.s_rsb.size = (size_t)value[3];
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dts_cfg.s_rsb.status = fdtdec_get_is_enabled(working_fdt, nodeoffset);
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ARISC_INF("s_rsb base:0x%p, size:0x%zx, status:%u\n",
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(void *)dts_cfg.s_rsb.base, dts_cfg.s_rsb.size, dts_cfg.s_rsb.status);
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/* parse s_jtag node */
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nodeoffset = fdt_node_offset_by_compatible(working_fdt, -1, "allwinner,s_jtag");
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if (IS_ERR_VALUE(nodeoffset)) {
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ARISC_ERR("get [allwinner,s_jtag] device node error\n");
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return -EINVAL;
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}
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dts_cfg.s_jtag.status = fdtdec_get_is_enabled(working_fdt, nodeoffset);
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ARISC_INF("s_jtag status:%u\n", dts_cfg.s_jtag.status);
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/* parse dvfs_table node */
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if (arisc_dvfs_cfg_vf_table()) {
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ARISC_ERR("parse dvfs v-f table failed\n");
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return -EINVAL;
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}
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/* parse s_cir node */
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nodeoffset = fdt_node_offset_by_compatible(working_fdt, -1, "allwinner,s_cir");
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if (IS_ERR_VALUE(nodeoffset)) {
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ARISC_ERR("get [allwinner,s_cir] device node error\n");
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return -EINVAL;
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}
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if (IS_ERR_VALUE(fdt_getprop_u32(working_fdt, nodeoffset, "ir_power_key_code", &dts_cfg.s_cir.power_key_code))) {
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ARISC_ERR("parse ir_power_key_code fail\n");
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return -EINVAL;
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}
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if (IS_ERR_VALUE(fdt_getprop_u32(working_fdt, nodeoffset, "ir_addr_code", &dts_cfg.s_cir.addr_code))) {
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ARISC_ERR("parse ir_addr_code fail\n");
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return -EINVAL;
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}
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ARISC_INF("scir ir_power_key_code:0x%x, ir_addr_code:0x%x\n",
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dts_cfg.s_cir.power_key_code, dts_cfg.s_cir.addr_code);
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/* config pmu config paras */
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nodeoffset = fdt_node_offset_by_compatible(working_fdt, -1, "allwinner,pmu0");
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if (IS_ERR_VALUE(nodeoffset)) {
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ARISC_ERR("get [allwinner,pmu0] device node error\n");
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return -EINVAL;
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}
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if (IS_ERR_VALUE(fdt_getprop_u32(working_fdt, nodeoffset, "pmu_bat_shutdown_ltf", &dts_cfg.pmu.pmu_bat_shutdown_ltf))) {
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ARISC_ERR("parse pmu_bat_shutdown_ltf fail\n");
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return -EINVAL;
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}
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if (IS_ERR_VALUE(fdt_getprop_u32(working_fdt, nodeoffset, "pmu_bat_shutdown_htf", &dts_cfg.pmu.pmu_bat_shutdown_htf))) {
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ARISC_ERR("parse pmu_bat_shutdown_htf fail\n");
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return -EINVAL;
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}
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if (IS_ERR_VALUE(fdt_getprop_u32(working_fdt, nodeoffset, "pmu_pwroff_vol", &dts_cfg.pmu.pmu_pwroff_vol))) {
|
|
ARISC_ERR("parse pmu_pwroff_vol fail\n");
|
|
return -EINVAL;
|
|
}
|
|
if (IS_ERR_VALUE(fdt_getprop_u32(working_fdt, nodeoffset, "power_start", &dts_cfg.pmu.power_start))) {
|
|
ARISC_ERR("parse power_start fail\n");
|
|
return -EINVAL;
|
|
}
|
|
ARISC_INF("pmu pmu_bat_shutdown_ltf:0x%x, pmu_bat_shutdown_htf:0x%x, pmu_pwroff_vol:0x%x, power_start:0x%x\n",
|
|
dts_cfg.pmu.pmu_bat_shutdown_ltf, dts_cfg.pmu.pmu_bat_shutdown_htf, dts_cfg.pmu.pmu_pwroff_vol, dts_cfg.pmu.power_start);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void sunxi_arisc_transform_cfg(void)
|
|
{
|
|
|
|
memcpy((void *)&dts_cfg_64.dram_para, (const void *)&dts_cfg.dram_para, sizeof(struct dram_para));
|
|
memcpy((void *)&dts_cfg_64.vf, (const void *)&dts_cfg.vf, sizeof(struct arisc_freq_voltage) * ARISC_DVFS_VF_TABLE_MAX);
|
|
|
|
dts_cfg_64.space.sram_dst = (u64)dts_cfg.space.sram_dst;
|
|
dts_cfg_64.space.sram_offset = (u64)dts_cfg.space.sram_offset;
|
|
dts_cfg_64.space.sram_size = (u64)dts_cfg.space.sram_size;
|
|
dts_cfg_64.space.dram_dst = (u64)dts_cfg.space.dram_dst;
|
|
dts_cfg_64.space.dram_offset = (u64)dts_cfg.space.dram_offset;
|
|
dts_cfg_64.space.dram_size = (u64)dts_cfg.space.dram_size;
|
|
dts_cfg_64.space.para_dst = (u64)dts_cfg.space.para_dst;
|
|
dts_cfg_64.space.para_offset = (u64)dts_cfg.space.para_offset;
|
|
dts_cfg_64.space.para_size = (u64)dts_cfg.space.para_size;
|
|
dts_cfg_64.space.msgpool_dst = (u64)dts_cfg.space.msgpool_dst;
|
|
dts_cfg_64.space.msgpool_offset = (u64)dts_cfg.space.msgpool_offset;
|
|
dts_cfg_64.space.msgpool_size = (u64)dts_cfg.space.msgpool_size;
|
|
dts_cfg_64.space.standby_dst = (u64)dts_cfg.space.standby_dst;
|
|
dts_cfg_64.space.standby_offset = (u64)dts_cfg.space.standby_offset;
|
|
dts_cfg_64.space.standby_size = (u64)dts_cfg.space.standby_size;
|
|
|
|
dts_cfg_64.image.base = (u64)dts_cfg.image.base;
|
|
dts_cfg_64.image.size = (u64)dts_cfg.image.size;
|
|
|
|
dts_cfg_64.prcm.base = (u64)dts_cfg.prcm.base;
|
|
dts_cfg_64.prcm.size = (u64)dts_cfg.prcm.size;
|
|
|
|
dts_cfg_64.cpuscfg.base = (u64)dts_cfg.cpuscfg.base;
|
|
dts_cfg_64.cpuscfg.size = (u64)dts_cfg.cpuscfg.size;
|
|
|
|
dts_cfg_64.msgbox.base = (u64)dts_cfg.msgbox.base;
|
|
dts_cfg_64.msgbox.size = (u64)dts_cfg.msgbox.size;
|
|
dts_cfg_64.msgbox.irq = dts_cfg.msgbox.irq;
|
|
dts_cfg_64.msgbox.status = dts_cfg.msgbox.status;
|
|
|
|
dts_cfg_64.hwspinlock.base = (u64)dts_cfg.hwspinlock.base;
|
|
dts_cfg_64.hwspinlock.size = (u64)dts_cfg.hwspinlock.size;
|
|
dts_cfg_64.hwspinlock.irq = dts_cfg.hwspinlock.irq;
|
|
dts_cfg_64.hwspinlock.status = dts_cfg.hwspinlock.status;
|
|
|
|
dts_cfg_64.s_uart.base = (u64)dts_cfg.s_uart.base;
|
|
dts_cfg_64.s_uart.size = (u64)dts_cfg.s_uart.size;
|
|
dts_cfg_64.s_uart.irq = dts_cfg.s_uart.irq;
|
|
dts_cfg_64.s_uart.status = dts_cfg.s_uart.status;
|
|
|
|
dts_cfg_64.s_rsb.base = (u64)dts_cfg.s_rsb.base;
|
|
dts_cfg_64.s_rsb.size = (u64)dts_cfg.s_rsb.size;
|
|
dts_cfg_64.s_rsb.irq = dts_cfg.s_rsb.irq;
|
|
dts_cfg_64.s_rsb.status = dts_cfg.s_rsb.status;
|
|
|
|
dts_cfg_64.s_jtag.base = (u64)dts_cfg.s_jtag.base;
|
|
dts_cfg_64.s_jtag.size = (u64)dts_cfg.s_jtag.size;
|
|
dts_cfg_64.s_jtag.irq = dts_cfg.s_jtag.irq;
|
|
dts_cfg_64.s_jtag.status = dts_cfg.s_jtag.status;
|
|
|
|
dts_cfg_64.s_cir.base = (u64)dts_cfg.s_cir.base;
|
|
dts_cfg_64.s_cir.size = (u64)dts_cfg.s_cir.size;
|
|
dts_cfg_64.s_cir.irq = dts_cfg.s_cir.irq;
|
|
dts_cfg_64.s_cir.status = dts_cfg.s_cir.status;
|
|
dts_cfg_64.s_cir.power_key_code = dts_cfg.s_cir.power_key_code;
|
|
dts_cfg_64.s_cir.addr_code = dts_cfg.s_cir.addr_code;
|
|
memcpy((void *)&dts_cfg_64.pmu, (const void *)&dts_cfg.pmu, sizeof(struct pmu_cfg));
|
|
memcpy((void *)&dts_cfg_64.power, (const void *)&dts_cfg.power, sizeof(struct power_cfg));
|
|
flush_dcache_range((unsigned long)&dts_cfg_64, ((unsigned long)&dts_cfg_64 + sizeof(struct dts_cfg_64)));
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
int sunxi_arisc_probe(void)
|
|
{
|
|
if(!sunxi_probe_secure_monitor())
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
ARISC_LOG("arisc initialize\n");
|
|
sunxi_arisc_parse_cfg();
|
|
|
|
/* because the uboot is arch32,
|
|
* and the runtime server is arch64,
|
|
* should transform the dts_cfg to dts_cfg_64.
|
|
*/
|
|
sunxi_arisc_transform_cfg();
|
|
|
|
if (arm_svc_arisc_startup((ulong)&dts_cfg_64)) {
|
|
/* arisc initialize failed */
|
|
ARISC_ERR("sunxi-arisc driver startup failed\n");
|
|
} else {
|
|
/* arisc initialize succeeded */
|
|
ARISC_LOG("sunxi-arisc driver startup succeeded\n");
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int sunxi_arisc_wait_ready(void)
|
|
{
|
|
if(get_boot_work_mode()!= WORK_MODE_BOOT)
|
|
{
|
|
return 0;
|
|
}
|
|
arm_svc_arisc_wait_ready();
|
|
return 0;
|
|
}
|
|
|
|
|