207 lines
9.9 KiB
C
207 lines
9.9 KiB
C
/*
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************************************************************************************************************************
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* eNand
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* Nand flash driver module config define
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*
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* Copyright(C), 2006-2008, SoftWinners Microelectronic Co., Ltd.
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* All Rights Reserved
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*
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* File Name : nand_boot.h
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*
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* Author : Kevin.z
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*
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* Version : v0.1
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*
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* Date : 2008.03.19
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*
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* Description : This file define the module config for nand flash driver.
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* if need support some module /
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* if need support some operation type /
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* config limit for some parameter. ex.
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*
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* Others : None at present.
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*
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*
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* History :
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*
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* <Author> <time> <version> <description>
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*
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* Kevin.z 2008.03.19 0.1 build the file
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*
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************************************************************************************************************************
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*/
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#ifndef __NAND_BOOT_H
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#define __NAND_BOOT_H
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#define STAMP_VALUE 0x5F0A6C39
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typedef struct
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{
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unsigned int ChannelCnt;
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unsigned int ChipCnt; //the count of the total nand flash chips are currently connecting on the CE pin
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unsigned int ChipConnectInfo; //chip connect information, bit == 1 means there is a chip connecting on the CE pin
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unsigned int RbCnt;
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unsigned int RbConnectInfo; //the connect information of the all rb chips are connected
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unsigned int RbConnectMode; //the rb connect mode
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unsigned int BankCntPerChip; //the count of the banks in one nand chip, multiple banks can support Inter-Leave
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unsigned int DieCntPerChip; //the count of the dies in one nand chip, block management is based on Die
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unsigned int PlaneCntPerDie; //the count of planes in one die, multiple planes can support multi-plane operation
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unsigned int SectorCntPerPage; //the count of sectors in one single physic page, one sector is 0.5k
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unsigned int PageCntPerPhyBlk; //the count of physic pages in one physic block
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unsigned int BlkCntPerDie; //the count of the physic blocks in one die, include valid block and invalid block
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unsigned int OperationOpt; //the mask of the operation types which current nand flash can support support
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unsigned int FrequencePar; //the parameter of the hardware access clock, based on 'MHz'
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unsigned int EccMode; //the Ecc Mode for the nand flash chip, 0: bch-16, 1:bch-28, 2:bch_32
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unsigned char NandChipId[8]; //the nand chip id of current connecting nand chip
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unsigned int ValidBlkRatio; //the ratio of the valid physical blocks, based on 1024
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unsigned int good_block_ratio; //good block ratio get from hwscan
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unsigned int ReadRetryType; //the read retry type
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unsigned int DDRType;
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unsigned int Reserved[32];
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}boot_nand_para_t;
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//ͨ<>õģ<C3B5><C4A3><EFBFBD>GPIO<49><4F>ص<EFBFBD><D8B5><EFBFBD><EFBFBD>ݽṹ
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typedef struct _normal_gpio_cfg
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{
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unsigned char port; //<2F>˿ں<CBBF>
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unsigned char port_num; //<2F>˿<EFBFBD><CBBF>ڱ<EFBFBD><DAB1>
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char mul_sel; //<2F><><EFBFBD>ܱ<EFBFBD><DCB1>
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char pull; //<2F><><EFBFBD><EFBFBD>״̬
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char drv_level; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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char data; //<2F><><EFBFBD><EFBFBD><EFBFBD>ƽ
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unsigned char reserved[2]; //<2F><><EFBFBD><EFBFBD>λ<EFBFBD><CEBB><EFBFBD><EFBFBD>֤<EFBFBD><D6A4><EFBFBD><EFBFBD>
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}normal_gpio_cfg;
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/******************************************************************************/
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/* head of Boot0 */
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/******************************************************************************/
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typedef struct _boot0_private_head_t
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{
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unsigned int prvt_head_size;
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char prvt_head_vsn[4]; // the version of boot0_private_head_t
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unsigned int dram_para[32]; // DRAM patameters for initialising dram. Original values is arbitrary,
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int uart_port; // UART<52><54><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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normal_gpio_cfg uart_ctrl[2]; // UART<52><54><EFBFBD><EFBFBD><EFBFBD><EFBFBD>(<28><><EFBFBD>Դ<EFBFBD>ӡ<EFBFBD><D3A1>)<29><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ
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int enable_jtag; // 1 : enable, 0 : disable
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normal_gpio_cfg jtag_gpio[5]; // <20><><EFBFBD><EFBFBD>JTAG<41><47>ȫ<EFBFBD><C8AB>GPIO<49><4F>Ϣ
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normal_gpio_cfg storage_gpio[32]; // <20>洢<EFBFBD>豸 GPIO<49><4F>Ϣ
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char storage_data[512 - sizeof(normal_gpio_cfg) * 32]; // <20>û<EFBFBD><C3BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ
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//boot_nand_connect_info_t nand_connect_info;
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}boot0_private_head_t;
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typedef struct standard_Boot_file_head
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{
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unsigned int jump_instruction; // one intruction jumping to real code
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unsigned char magic[8]; // ="eGON.BT0" or "eGON.BT1", not C-style string.
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unsigned int check_sum; // generated by PC
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unsigned int length; // generated by PC
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unsigned int pub_head_size; // the size of boot_file_head_t
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unsigned char pub_head_vsn[4]; // the version of boot_file_head_t
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unsigned char file_head_vsn[4]; // the version of boot0_file_head_t or boot1_file_head_t
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unsigned char Boot_vsn[4]; // Boot version
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unsigned char eGON_vsn[4]; // eGON version
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unsigned char platform[8]; // platform information
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}standard_boot_file_head_t;
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typedef struct _boot0_file_head_t
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{
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standard_boot_file_head_t boot_head;
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boot0_private_head_t prvt_head;
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}boot0_file_head_t;
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typedef struct _boot_core_para_t
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{
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unsigned int user_set_clock; // <20><><EFBFBD><EFBFBD>Ƶ<EFBFBD><C6B5> M<><4D>λ
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unsigned int user_set_core_vol; // <20><><EFBFBD>ĵ<EFBFBD>ѹ mV<6D><56>λ
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unsigned int vol_threshold; // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѹ
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}boot_core_para_t;
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/******************************************************************************/
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/* head of Boot1 */
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/******************************************************************************/
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typedef struct _boot1_private_head_t
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{
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unsigned int dram_para[32];
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int run_clock; // Mhz
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int run_core_vol; // mV
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int uart_port; // UART<52><54><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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normal_gpio_cfg uart_gpio[2]; // UART<52><54><EFBFBD><EFBFBD><EFBFBD><EFBFBD>(<28><><EFBFBD>Դ<EFBFBD>ӡ<EFBFBD><D3A1>)GPIO<49><4F>Ϣ
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int twi_port; // TWI<57><49><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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normal_gpio_cfg twi_gpio[2]; // TWI<57><49><EFBFBD><EFBFBD><EFBFBD><EFBFBD>GPIO<49><4F>Ϣ<EFBFBD><CFA2><EFBFBD><EFBFBD><EFBFBD>ڿ<EFBFBD><DABF><EFBFBD>TWI
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int work_mode; // <20><><EFBFBD><EFBFBD>ģʽ
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int storage_type; // <20>洢<EFBFBD><E6B4A2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 0<><30>nand 1<><31>sdcard 2: spinor
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normal_gpio_cfg nand_gpio[32]; // nand GPIO<49><4F>Ϣ
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char nand_spare_data[256]; // nand <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ
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normal_gpio_cfg sdcard_gpio[32]; // sdcard GPIO<49><4F>Ϣ
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char sdcard_spare_data[256]; // sdcard <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ
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int reserved[6]; // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ, 256bytes align
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}boot1_private_head_t;
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typedef struct _Boot_file_head
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{
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unsigned int jump_instruction; // one intruction jumping to real code
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unsigned char magic[8]; // ="u-boot"
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unsigned int check_sum; // generated by PC
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unsigned int align_size; // align size in byte
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unsigned int length; // the size of all file
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unsigned int uboot_length; // the size of uboot
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unsigned char version[8]; // uboot version
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unsigned char platform[8]; // platform information
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int reserved[1]; //stamp space, 16bytes align
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}boot_file_head_t;
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typedef struct _boot1_file_head_t
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{
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boot_file_head_t boot_head;
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boot1_private_head_t prvt_head;
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}boot1_file_head_t;
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typedef struct sbrom_toc0_config
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{
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unsigned char config_vsn[4];
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unsigned int dram_para[32]; // dram<61><6D><EFBFBD><EFBFBD>
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int uart_port; // UART<52><54><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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normal_gpio_cfg uart_ctrl[2]; // UART<52><54><EFBFBD><EFBFBD><EFBFBD><EFBFBD>GPIO
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int enable_jtag; // JTAGʹ<47><CAB9>
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normal_gpio_cfg jtag_gpio[5]; // JTAG<41><47><EFBFBD><EFBFBD><EFBFBD><EFBFBD>GPIO
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normal_gpio_cfg storage_gpio[50]; // <20>洢<EFBFBD>豸 GPIO<49><4F>Ϣ
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// 0-23<32><33>nand<6E><64>24-31<33><31>ſ<EFBFBD>0<EFBFBD><30>32-39<33>ſ<EFBFBD>2
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// 40-49<34><39><EFBFBD>spi
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char storage_data[384]; // 0-159,<2C>洢nand<6E><64>Ϣ<EFBFBD><CFA2>160-255,<2C><>ſ<EFBFBD><C5BF><EFBFBD>Ϣ
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unsigned int secure_dram_mbytes; //
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unsigned int drm_start_mbytes; //
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unsigned int drm_size_mbytes; //
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unsigned int res[8]; // <20>ܹ<EFBFBD>1024<32>ֽ<EFBFBD>
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}sbrom_toc0_config_t;
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typedef struct
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{
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u8 name[8]; //<2F>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ը<EFBFBD><D4B8>ģ<EFBFBD>û<EFBFBD><C3BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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u32 magic; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>0x89119800
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u32 check_sum; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݵ<EFBFBD>У<EFBFBD><D0A3>ͣ<EFBFBD><CDA3>ο<EFBFBD><CEBF><EFBFBD><EFBFBD><EFBFBD>boot0<74><30><EFBFBD><EFBFBD>
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u32 serial_num; //<2F><><EFBFBD>кţ<D0BA><C5A3><EFBFBD><EFBFBD>Ը<EFBFBD><D4B8>ģ<EFBFBD>û<EFBFBD><C3BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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u32 status; //<2F><><EFBFBD>Ը<EFBFBD><D4B8>ģ<EFBFBD>û<EFBFBD><C3BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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u32 items_nr; //<2F>ܵ<EFBFBD><DCB5><EFBFBD>Ŀ<EFBFBD><C4BF><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>TOC0<43><30>˵<EFBFBD><CBB5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>2
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u32 length; //TOC0<43>ij<EFBFBD><C4B3><EFBFBD>
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u8 platform[4]; //toc_platform[0]<5D><>ʾ<EFBFBD><CABE><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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//0<><30>nand<6E><64>1<EFBFBD><31><EFBFBD><EFBFBD>0<EFBFBD><30>2<EFBFBD><32><EFBFBD><EFBFBD>2<EFBFBD><32>3<EFBFBD><33>spinor
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u32 reserved[2]; //<2F><><EFBFBD><EFBFBD>λ
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u32 end; //<2F><>ʾͷ<CABE><CDB7><EFBFBD>ṹ<EFBFBD><E1B9B9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>0x3b45494d
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}toc0_private_head_t;
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#define SBROM_TOC0_HEAD_SPACE 0x80
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#endif //ifndef __NAND_DRV_CFG_H
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