272 lines
14 KiB
C
Executable File
272 lines
14 KiB
C
Executable File
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#ifndef _LINUX_SCENELOCK_DATA_SUN8IW1P1_H
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#define _LINUX_SCENELOCK_DATA_SUN8IW1P1_H
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#include <linux/power/axp_depend.h>
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scene_extended_standby_t extended_standby[] = {
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{
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.scene_type = SCENE_TALKING_STANDBY,
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.name = "talking_standby",
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.soc_pwr_dep.id = TALKING_STANDBY_FLAG,
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//mean dram, cpus,dram_pll,vcc_pl, vcc_io, vcc_ldoin is on.
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//note: vcc_pm is marked on, just for cross-platform reason.
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//at a83: with the sys_mask's help, we know we do not need care about vcc_pm state.
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.soc_pwr_dep.soc_pwr_dm_state.state = BITMAP(VCC_DRAM_BIT) | BITMAP(VDD_CPUS_BIT) |\
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BITMAP(VDD_DRAMPLL_BIT) | BITMAP(VCC_PL_BIT) | \
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BITMAP(VCC_PM_BIT) | BITMAP(VCC_LDOIN_BIT),
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.soc_pwr_dep.soc_pwr_dm_state.volt[0] = 0x0, //mean: donot need care about the voltage.
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.soc_pwr_dep.cpux_clk_state.osc_en = 0x0, // mean all osc is off.
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.soc_pwr_dep.cpux_clk_state.init_pll_dis = BITMAP(PM_PLL_DRAM), //mean pll5 is shutdowned & open by dram driver.
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.soc_pwr_dep.cpux_clk_state.exit_pll_en = 0x0,
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.soc_pwr_dep.cpux_clk_state.pll_change = 0x0,
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.soc_pwr_dep.cpux_clk_state.bus_change = 0x0,
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.soc_pwr_dep.soc_dram_state.selfresh_flag = 0x1,
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.soc_pwr_dep.soc_io_state.hold_flag = 0x1,
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//for pf port: set the io to disable state.;
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.soc_pwr_dep.soc_io_state.io_state[0] = {(unsigned int *)0x01c208b4, 0x00f0f0ff, 0x00707077},
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.soc_pwr_dep.soc_io_state.io_state[1] = {(unsigned int *)0x01c208b4, 0x000f0f00, 0x00070700},
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#if 0
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//for pb port
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.soc_pwr_dep.soc_io_state.io_state[0] = {(unsigned int *)0x01c20824, 0x0000ffff, 0x00007777},
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.soc_pwr_dep.soc_io_state.io_state[1] = {(unsigned int *)0x01c20828, 0x00000ff0, 0x00000770},
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#endif
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},
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{
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.scene_type = SCENE_USB_STANDBY,
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.name = "usb_standby",
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.soc_pwr_dep.id = USB_STANDBY_FLAG,
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//mean dram, cpus,dram_pll,vcc_pl, vcc_ldoin, vdd_sys is on.
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//note: vcc_pm is marked on, just for cross-platform reason.
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//at a83: with the sys_mask's help, we know we do not need care about vcc_pm state.
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.soc_pwr_dep.soc_pwr_dm_state.state = BITMAP(VCC_DRAM_BIT) | BITMAP(VDD_CPUS_BIT) |\
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BITMAP(VDD_DRAMPLL_BIT) | BITMAP(VCC_PL_BIT) | \
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BITMAP(VCC_PM_BIT) | BITMAP(VCC_LDOIN_BIT) |\
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BITMAP(VDD_SYS_BIT),
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.soc_pwr_dep.soc_pwr_dm_state.volt[0] = 0x0, //mean: donot need care about the voltage.
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.soc_pwr_dep.cpux_clk_state.osc_en = BITMAP(OSC_LOSC_BIT) | BITMAP(OSC_HOSC_BIT), // mean all osc is off. +losc, +hosc
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.soc_pwr_dep.cpux_clk_state.init_pll_dis = BITMAP(PM_PLL_DRAM), //mean pll5 is shutdowned & open by dram driver.
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.soc_pwr_dep.cpux_clk_state.exit_pll_en = 0x0,
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.soc_pwr_dep.cpux_clk_state.pll_change = BITMAP(PM_PLL_PERIPH),
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.soc_pwr_dep.cpux_clk_state.pll_factor[PM_PLL_PERIPH] = { //PLL_PERIPH freq = 24*12/2/2= 72M
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.factor1 = 12, //N=12
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.factor2 = 1, //Div1 = 1 + 1 = 2
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.factor3 = 1, //Div2 = 1 + 1 = 2
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},
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.soc_pwr_dep.cpux_clk_state.bus_change = BITMAP(BUS_AHB1) | BITMAP(BUS_AHB2),
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.soc_pwr_dep.cpux_clk_state.bus_factor[BUS_AHB1] = {
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.src = CLK_SRC_LOSC, //need make sure losc is on.
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.pre_div = 0,
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.div_ratio = 0,
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},
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.soc_pwr_dep.cpux_clk_state.bus_factor[BUS_AHB2] = {
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.src = CLK_SRC_AHB1, //need make sure AHB1 is on.
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.pre_div = 0,
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.div_ratio = 0,
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},
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.soc_pwr_dep.soc_dram_state.selfresh_flag = 0x1,
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.soc_pwr_dep.soc_io_state.hold_flag = 0x0,
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//for pf port: set the io to disable state.;
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.soc_pwr_dep.soc_io_state.io_state[0] = {(unsigned int *)0x01c208b4, 0x00f0f0ff, 0x00707077},
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.soc_pwr_dep.soc_io_state.io_state[1] = {(unsigned int *)0x01c208b4, 0x000f0f00, 0x00070700},
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},
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{
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.scene_type = SCENE_MP3_STANDBY,
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.name = "mp3_standby",
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.soc_pwr_dep.id = MP3_STANDBY_FLAG,
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},
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{
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.scene_type = SCENE_BOOT_FAST,
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.name = "boot_fast",
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.soc_pwr_dep.id = BOOT_FAST_STANDBY_FLAG,
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},
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{
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.scene_type = SCENE_SUPER_STANDBY,
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.name = "super_standby",
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.soc_pwr_dep.id = SUPER_STANDBY_FLAG,
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//mean dram, cpus,dram_pll,vcc_pl, vcc_io, vcc_ldoin is on.
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//note: vcc_pm is marked on, just for cross-platform reason.
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//at a83: with the sys_mask's help, we know we do not need care about vcc_pm state.
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.soc_pwr_dep.soc_pwr_dm_state.state = BITMAP(VCC_DRAM_BIT) | BITMAP(VDD_CPUS_BIT) |\
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BITMAP(VDD_DRAMPLL_BIT) | BITMAP(VCC_PL_BIT) | \
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BITMAP(VCC_PM_BIT) | BITMAP(VCC_LDOIN_BIT),
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//mean care about cpua, dram, sys, cpus, dram_pll, vdd_adc, vcc_pl, vcc_io, vcc_cpvdd, vcc_ldoin, vcc_pll
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.soc_pwr_dep.soc_pwr_dm_state.volt[0] = 0x0, //mean: donot need care about the voltage.
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.soc_pwr_dep.cpux_clk_state.osc_en = 0x0, // mean all osc is off.
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.soc_pwr_dep.cpux_clk_state.init_pll_dis = BITMAP(PM_PLL_DRAM), //mean pll5 is shutdowned & open by dram driver.
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.soc_pwr_dep.cpux_clk_state.exit_pll_en = 0x0,
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.soc_pwr_dep.cpux_clk_state.pll_change = 0x0,
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.soc_pwr_dep.cpux_clk_state.bus_change = 0x0,
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.soc_pwr_dep.soc_dram_state.selfresh_flag = 0x1,
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.soc_pwr_dep.soc_io_state.hold_flag = 0x1,
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//for pf port: set the io to disable state.;
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.soc_pwr_dep.soc_io_state.io_state[0] = {(unsigned int *)0x01c208b4, 0x00f0f0ff, 0x00707077},
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.soc_pwr_dep.soc_io_state.io_state[1] = {(unsigned int *)0x01c208b4, 0x000f0f00, 0x00070700},
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},
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{
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.scene_type = SCENE_GPIO_HOLD_STANDBY,
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.name = "gpio_hold_standby",
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.soc_pwr_dep.id = GPIO_HOLD_STANDBY_FLAG,
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//mean dram, cpus,dram_pll,vcc_pl, vcc_io, vcc_ldoin is on.
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//note: vcc_pm is marked on, just for cross-platform reason.
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//at a83: with the sys_mask's help, we know we do not need care about vcc_pm state.
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.soc_pwr_dep.soc_pwr_dm_state.state = BITMAP(VCC_DRAM_BIT) | BITMAP(VDD_CPUS_BIT) |\
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BITMAP(VDD_DRAMPLL_BIT) | BITMAP(VCC_PL_BIT) | \
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BITMAP(VCC_PM_BIT) | BITMAP(VCC_IO_BIT) | BITMAP(VCC_LDOIN_BIT),
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//mean care about cpua, dram, sys, cpus, dram_pll, vdd_adc, vcc_pl, vcc_io, vcc_cpvdd, vcc_ldoin, vcc_pll
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.soc_pwr_dep.soc_pwr_dm_state.volt[0] = 0x0, //mean: donot need care about the voltage.
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.soc_pwr_dep.cpux_clk_state.osc_en = 0x0, // mean all osc is off.
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.soc_pwr_dep.cpux_clk_state.init_pll_dis = BITMAP(PM_PLL_DRAM), //mean pll5 is shutdowned & open by dram driver.
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.soc_pwr_dep.cpux_clk_state.exit_pll_en = 0x0,
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.soc_pwr_dep.cpux_clk_state.pll_change = 0x0,
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.soc_pwr_dep.cpux_clk_state.bus_change = 0x0,
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.soc_pwr_dep.soc_dram_state.selfresh_flag = 0x1,
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.soc_pwr_dep.soc_io_state.hold_flag = 0x1,
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//for pf port: set the io to disable state.;
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.soc_pwr_dep.soc_io_state.io_state[0] = {(unsigned int *)0x01c208b4, 0x00f0f0ff, 0x00707077},
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.soc_pwr_dep.soc_io_state.io_state[1] = {(unsigned int *)0x01c208b4, 0x000f0f00, 0x00070700},
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},
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{
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.scene_type = SCENE_NORMAL_STANDBY,
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.name = "normal_standby",
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.soc_pwr_dep.id = NORMAL_STANDBY_FLAG,
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//mean dram, cpus,dram_pll,vcc_pl, vcc_io, vcc_ldoin is on.
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//note: vcc_pm is marked on, just for cross-platform reason.
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//at a83: with the sys_mask's help, we know we do not need care about vcc_pm state.
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.soc_pwr_dep.soc_pwr_dm_state.state = BITMAP(VCC_DRAM_BIT) | BITMAP(VDD_CPUS_BIT) |\
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BITMAP(VDD_DRAMPLL_BIT) | BITMAP(VCC_PL_BIT) | \
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BITMAP(VCC_PM_BIT) | BITMAP(VCC_LDOIN_BIT),
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//mean care about cpua, dram, sys, cpus, dram_pll, vdd_adc, vcc_pl, vcc_io, vcc_cpvdd, vcc_ldoin, vcc_pll
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.soc_pwr_dep.soc_pwr_dm_state.volt[0] = 0x0, //mean: donot need care about the voltage.
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.soc_pwr_dep.cpux_clk_state.osc_en = 0x0, // mean all osc is off.
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.soc_pwr_dep.cpux_clk_state.init_pll_dis = BITMAP(PM_PLL_DRAM), //mean pll5 is shutdowned & open by dram driver.
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.soc_pwr_dep.cpux_clk_state.exit_pll_en = 0x0,
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.soc_pwr_dep.cpux_clk_state.pll_change = 0x0,
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.soc_pwr_dep.cpux_clk_state.bus_change = 0x0,
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.soc_pwr_dep.soc_dram_state.selfresh_flag = 0x1,
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.soc_pwr_dep.soc_io_state.hold_flag = 0x1,
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//for pf port: set the io to disable state.;
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.soc_pwr_dep.soc_io_state.io_state[0] = {(unsigned int *)0x01c208b4, 0x00f0f0ff, 0x00707077},
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.soc_pwr_dep.soc_io_state.io_state[1] = {(unsigned int *)0x01c208b4, 0x000f0f00, 0x00070700},
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},
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{
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.scene_type = SCENE_GPIO_STANDBY,
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.name = "gpio_standby",
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.soc_pwr_dep.id = GPIO_STANDBY_FLAG,
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//mean dram, cpus,dram_pll,vcc_pl, vcc_io, vcc_ldoin is on. +vdd_sys
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//note: vcc_pm is marked on, just for cross-platform reason.
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//at a83: with the sys_mask's help, we know we do not need care about vcc_pm state.
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.soc_pwr_dep.soc_pwr_dm_state.state = BITMAP(VCC_DRAM_BIT) | BITMAP(VDD_CPUS_BIT) |\
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BITMAP(VDD_SYS_BIT) | BITMAP(VDD_DRAMPLL_BIT) | BITMAP(VCC_PL_BIT) | \
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BITMAP(VCC_PM_BIT) | BITMAP(VCC_IO_BIT) | BITMAP(VCC_LDOIN_BIT),
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//mean care about cpua, dram, sys, cpus, dram_pll, vdd_adc, vcc_pl, vcc_io, vcc_cpvdd, vcc_ldoin, vcc_pll
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.soc_pwr_dep.soc_pwr_dm_state.volt[0] = 0x0, //mean: donot need care about the voltage.
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.soc_pwr_dep.cpux_clk_state.osc_en = BITMAP(OSC_LOSC_BIT), // mean all osc is off. +losc
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.soc_pwr_dep.cpux_clk_state.init_pll_dis = BITMAP(PM_PLL_DRAM), //mean pll5 is shutdowned & open by dram driver.
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.soc_pwr_dep.cpux_clk_state.exit_pll_en = 0x0,
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.soc_pwr_dep.cpux_clk_state.pll_change = 0x0,
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.soc_pwr_dep.cpux_clk_state.bus_change = BITMAP(BUS_AHB1),
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.soc_pwr_dep.cpux_clk_state.bus_factor[BUS_AHB1] = {
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.src = CLK_SRC_LOSC, //need make sure losc is on.
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.pre_div = 0,
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.div_ratio = 0,
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},
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.soc_pwr_dep.soc_dram_state.selfresh_flag = 0x1,
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.soc_pwr_dep.soc_io_state.hold_flag = 0x0,
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//for pf port: set the io to disable state.;
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.soc_pwr_dep.soc_io_state.io_state[0] = {(unsigned int *)0x01c208b4, 0x00f0f0ff, 0x00707077},
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.soc_pwr_dep.soc_io_state.io_state[1] = {(unsigned int *)0x01c208b4, 0x000f0f00, 0x00070700},
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#if 0
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//for pb port
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.soc_pwr_dep.soc_io_state.io_state[0] = {(unsigned int *)0x01c20824, 0x0000ffff, 0x00007777},
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.soc_pwr_dep.soc_io_state.io_state[1] = {(unsigned int *)0x01c20828, 0x00000ff0, 0x00000770},
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#endif
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},
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{
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.scene_type = SCENE_MISC_STANDBY,
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.name = "misc_standby",
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.soc_pwr_dep.id = MISC_STANDBY_FLAG,
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//mean dram, cpus,dram_pll,vcc_pl, vcc_io, vcc_ldoin is on.
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//note: vcc_pm is marked on, just for cross-platform reason.
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//at a83: with the sys_mask's help, we know we do not need care about vcc_pm state.
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.soc_pwr_dep.soc_pwr_dm_state.state = BITMAP(VCC_DRAM_BIT) | BITMAP(VDD_CPUS_BIT) |\
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BITMAP(VCC_PL_BIT) | \
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BITMAP(VCC_PM_BIT) | BITMAP(VCC_IO_BIT) ,
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0x0644, //-vcc_io; -dram, ldoin/ adc/ cpvdd
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//mean care about cpua, dram, sys, cpus, dram_pll, vdd_adc, vcc_pl, vcc_io, vcc_cpvdd, vcc_ldoin, vcc_pll
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.soc_pwr_dep.soc_pwr_dm_state.volt[0] = 0x0, //mean: donot need care about the voltage.
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.soc_pwr_dep.cpux_clk_state.osc_en = 0x0, // mean all osc is off.
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.soc_pwr_dep.cpux_clk_state.init_pll_dis = (~(0x20)), //mean pll5 is shutdowned & open by dram driver.
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.soc_pwr_dep.cpux_clk_state.exit_pll_en = 0x0,
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.soc_pwr_dep.cpux_clk_state.pll_change = 0x0,
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.soc_pwr_dep.cpux_clk_state.bus_change = 0x0,
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.soc_pwr_dep.soc_dram_state.selfresh_flag = 0x1,
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.soc_pwr_dep.soc_io_state.hold_flag = 0x1,
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//for pf port: set the io to disable state.;
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.soc_pwr_dep.soc_io_state.io_state[0] = {(unsigned int *)0x01c208b4, 0x00f0f0ff, 0x00707077},
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.soc_pwr_dep.soc_io_state.io_state[1] = {(unsigned int *)0x01c208b4, 0x000f0f00, 0x00070700},
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},
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{
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.scene_type = SCENE_MISC1_STANDBY,
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.name = "misc1_standby",
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.soc_pwr_dep.id = MISC1_STANDBY_FLAG,
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//mean dram, cpus,dram_pll,vcc_pl, vcc_io, vcc_ldoin is on.
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//note: vcc_pm is marked on, just for cross-platform reason.
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//at a83: with the sys_mask's help, we know we do not need care about vcc_pm state.
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.soc_pwr_dep.soc_pwr_dm_state.state = BITMAP(VCC_DRAM_BIT) | BITMAP(VDD_CPUS_BIT) |\
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BITMAP(VCC_PL_BIT) | \
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BITMAP(VCC_PM_BIT),
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//mean care about cpua, dram, sys, cpus, dram_pll, vdd_adc, vcc_pl, vcc_io, vcc_cpvdd, vcc_ldoin, vcc_pll
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.soc_pwr_dep.soc_pwr_dm_state.volt[0] = 0x0, //mean: donot need care about the voltage.
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.soc_pwr_dep.cpux_clk_state.osc_en = 0x0, // mean all osc is off.
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.soc_pwr_dep.cpux_clk_state.init_pll_dis = (~(0x20)), //mean pll5 is shutdowned & open by dram driver.
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.soc_pwr_dep.cpux_clk_state.exit_pll_en = 0x0,
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.soc_pwr_dep.cpux_clk_state.pll_change = 0x0,
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.soc_pwr_dep.cpux_clk_state.bus_change = 0x0,
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.soc_pwr_dep.soc_dram_state.selfresh_flag = 0x1,
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.soc_pwr_dep.soc_io_state.hold_flag = 0x1, //hold gpio
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//for pf port: set the io to disable state.;
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.soc_pwr_dep.soc_io_state.io_state[0] = {(unsigned int *)0x01c208b4, 0x00f0f0ff, 0x00707077},
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.soc_pwr_dep.soc_io_state.io_state[1] = {(unsigned int *)0x01c208b4, 0x000f0f00, 0x00070700},
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},
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{
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//for parse sysconfig config. //
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//default config according dram enter selfresh.
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//when not enable enter selfresh, need open vdd_sys.
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.scene_type = SCENE_DYNAMIC_STANDBY,
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.name = "dynamic_standby",
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.soc_pwr_dep.id = DYNAMIC_STANDBY_FLAG,
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//mean dram, cpus,dram_pll,vcc_pl, vcc_io, vcc_ldoin is on.
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//note: vcc_pm is marked on, just for cross-platform reason.
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//at a83: with the sys_mask's help, we know we do not need care about vcc_pm state.
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.soc_pwr_dep.soc_pwr_dm_state.state = BITMAP(VCC_DRAM_BIT) | BITMAP(VDD_CPUS_BIT) |\
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BITMAP(VDD_DRAMPLL_BIT) | BITMAP(VCC_PL_BIT) | \
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BITMAP(VCC_PM_BIT) | BITMAP(VCC_LDOIN_BIT) | \
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BITMAP(VDD_SYS_BIT)| BITMAP(VDD_CPUA_BIT),
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//mean care about cpua, dram, sys, cpus, dram_pll, vdd_adc, vcc_pl, vcc_io, vcc_cpvdd, vcc_ldoin, vcc_pll
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.soc_pwr_dep.soc_pwr_dm_state.volt[0] = 0x0, //mean: donot need care about the voltage.
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.soc_pwr_dep.cpux_clk_state.osc_en = 0x0, // mean all osc is off.
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.soc_pwr_dep.cpux_clk_state.init_pll_dis = (BITMAP(PM_PLL_DRAM)), //mean pll5 is shutdowned & open by dram driver.
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.soc_pwr_dep.cpux_clk_state.exit_pll_en = 0x0,
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.soc_pwr_dep.cpux_clk_state.pll_change = 0x0,
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.soc_pwr_dep.cpux_clk_state.bus_change = 0x0,
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.soc_pwr_dep.soc_dram_state.selfresh_flag = 0x1, //enter selfresh, for compatible reason.
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.soc_pwr_dep.soc_io_state.hold_flag = 0x1,
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//for pf port: set the io to disable state.;
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.soc_pwr_dep.soc_io_state.io_state[0] = {(unsigned int *)0x01c208b4, 0x00f0f0ff, 0x00707077},
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.soc_pwr_dep.soc_io_state.io_state[1] = {(unsigned int *)0x01c208b4, 0x000f0f00, 0x00070700},
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},
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};
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#endif
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