175 lines
5.0 KiB
C
Executable File
175 lines
5.0 KiB
C
Executable File
#ifndef _MEM_CPU_H
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#define _MEM_CPU_H
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/*
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* Copyright (c) 2011-2015 yanggq.young@allwinnertech.com
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*/
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/*
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* Image of the saved processor state
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*
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* coprocessor 15 registers(RW)
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*/
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struct saved_context {
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/*
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* FIXME: Only support for Cortex A8 and Cortex A9 now
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*/
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/* CR0 */
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__u32 cssr; /* Cache Size Selection */
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/* CR1 */
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#ifdef CORTEX_A8
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__u32 cr; /* Control */
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__u32 acr; /* Auxiliary Control Register*/
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__u32 cacr; /* Coprocessor Access Control */
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__u32 sccfgr; /* Secure Config Register*/
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__u32 scdbgenblr; /* Secure Debug Enable Register*/
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__u32 nonscacctrlr;/* Nonsecure Access Control Register*/
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#elif defined(CORTEX_A9)
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__u32 cr;
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__u32 actlr;
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__u32 cacr;
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__u32 sder;
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__u32 vcr;
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#elif defined(CORTEX_A7)
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__u32 cr; /* Control */
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__u32 acr; /* Auxiliary Control Register*/
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__u32 cacr; /* Coprocessor Access Control */
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__u32 sccfgr; /* Secure Config Register*/
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__u32 scdbgenblr; /* Secure Debug Enable Register*/
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__u32 nonscacctrlr;/* Nonsecure Access Control Register*/
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#endif
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/* CR2 */
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__u32 ttb_0r; /* Translation Table Base 0 */
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__u32 ttb_1r; /* Translation Table Base 1 */
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__u32 ttbcr; /* Translation Talbe Base Control */
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/* CR3 */
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__u32 dacr; /* Domain Access Control */
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/* CR5 */
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__u32 d_fsr; /* Data Fault Status */
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__u32 i_fsr; /* Instruction Fault Status */
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__u32 d_afsr; /* Data Auxilirary Fault Status */ ;
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__u32 i_afsr; /* Instruction Auxilirary Fault Status */;
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/* CR6 */
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__u32 d_far; /* Data Fault Address */
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__u32 i_far; /* Instruction Fault Address */
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/* CR7 */
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__u32 par; /* Physical Address */
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/* CR9 */ /* FIXME: Are they necessary? */
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__u32 pmcontrolr; /* Performance Monitor Control */
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__u32 cesr; /* Count Enable Set */
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__u32 cecr; /* Count Enable Clear */
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__u32 ofsr; /* Overflow Flag Status */
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#ifdef CORTEX_A8
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__u32 sir; /* Software Increment */
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#elif defined(CORTEX_A7)
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__u32 sir; /* Software Increment */
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#endif
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__u32 pcsr; /* Performance Counter Selection */
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__u32 ccr; /* Cycle Count */
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__u32 esr; /* Event Selection */
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__u32 pmcountr; /* Performance Monitor Count */
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__u32 uer; /* User Enable */
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__u32 iesr; /* Interrupt Enable Set */
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__u32 iecr; /* Interrupt Enable Clear */
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#ifdef CORTEX_A8
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__u32 l2clr; /* L2 Cache Lockdown */
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__u32 l2cauxctrlr; /* L2 Cache Auxiliary Control */
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#elif defined(CORTEX_A7)
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#endif
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/* CR10 */
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#ifdef CORTEX_A8
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__u32 d_tlblr; /* Data TLB Lockdown Register */
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__u32 i_tlblr; /* Instruction TLB Lockdown Register */
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#elif defined(CORTEX_A7)
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#endif
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__u32 prrr; /* Primary Region Remap Register */
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__u32 nrrr; /* Normal Memory Remap Register */
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/* CR11 */
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#ifdef CORTEX_A8
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__u32 pleuar; /* PLE User Accessibility */
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__u32 plecnr; /* PLE Channel Number */
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__u32 plecr; /* PLE Control */
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__u32 pleisar; /* PLE Internal Start Address */
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__u32 pleiear; /* PLE Internal End Address */
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__u32 plecidr; /* PLE Context ID */
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#elif defined(CORTEX_A7)
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#endif
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/* CR12 */
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#ifdef CORTEX_A8
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__u32 snsvbar; /* Secure or Nonsecure Vector Base Address */
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__u32 monvecbar; /*Monitor Vector Base*/
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#elif defined(CORTEX_A9)
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__u32 vbar;
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__u32 mvbar;
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__u32 vir;
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#elif defined(CORTEX_A7)
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__u32 vbar;
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__u32 mvbar;
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__u32 isr;
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#endif
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/* CR13 */
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__u32 fcse; /* FCSE PID */
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__u32 cid; /* Context ID */
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__u32 urwtpid; /* User read/write Thread and Process ID */
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__u32 urotpid; /* User read-only Thread and Process ID */
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__u32 potpid; /* Privileged only Thread and Process ID */
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/* CR15 */
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#ifdef CORTEX_A9
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__u32 mtlbar;
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#endif
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} __attribute__((packed));
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void __save_processor_state(struct saved_context *ctxt);
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void __restore_processor_state(struct saved_context *ctxt);
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void disable_cache_invalidate(void);
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void set_copro_default(void);
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void save_processor_state(void);
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void restore_processor_state(void);
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void restore_processor_ttbr0(void);
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void set_ttbr0(void);
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extern int get_cur_cluster_id(void);
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/* Used in mem_cpu_asm.S */
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#define SYS_CONTEXT_SIZE (2)
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#define SVC_CONTEXT_SIZE (2) //do not need backup r14? reason?
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#define FIQ_CONTEXT_SIZE (7)
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#define ABT_CONTEXT_SIZE (2 )
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#define IRQ_CONTEXT_SIZE (2)
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#define UND_CONTEXT_SIZE (2)
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#define MON_CONTEXT_SIZE (2)
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#define EMPTY_CONTEXT_SIZE (11 * sizeof(__u32))
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extern unsigned long saved_context_r13_sys[SYS_CONTEXT_SIZE];
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extern unsigned long saved_cpsr_svc;
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extern unsigned long saved_context_r12_svc[SVC_CONTEXT_SIZE];
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extern unsigned long saved_spsr_svc;
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extern unsigned long saved_context_r13_fiq[FIQ_CONTEXT_SIZE];
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extern unsigned long saved_spsr_fiq;
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extern unsigned long saved_context_r13_abt[ABT_CONTEXT_SIZE];
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extern unsigned long saved_spsr_abt;
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extern unsigned long saved_context_r13_irq[IRQ_CONTEXT_SIZE];
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extern unsigned long saved_spsr_irq;
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extern unsigned long saved_context_r13_und[UND_CONTEXT_SIZE];
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extern unsigned long saved_spsr_und;
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extern unsigned long saved_context_r13_mon[MON_CONTEXT_SIZE];
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extern unsigned long saved_spsr_mon;
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extern unsigned long saved_empty_context_svc[EMPTY_CONTEXT_SIZE];
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#endif /*_MEM_CPU_H*/
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