292 lines
18 KiB
C
292 lines
18 KiB
C
/*
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* arch/arm/mach-sunxi/pm/ccmu-sun50iw1p1.h
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*
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* Copyright 2012 (c) njubietech.
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* gq.yang (yanggq@njubietech.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef __MEM_CCMU_SUN8W10P1_H__
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#define __MEM_CCMU_SUN8W10P1_H__
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typedef union{
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__u32 dwval;
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struct
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{
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__u32 FactorM:2; //bit0, PLL1 Factor M
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__u32 reserved0:2; //bit2, reserved
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__u32 FactorK:2; //bit4, PLL1 factor K
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__u32 reserved1:2; //bit6, reserved
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__u32 FactorN:5; //bit8, PLL1 Factor N
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__u32 reserved2:3; //bit13, reserved
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__u32 FactorP:2; //bit16, PLL1 Factor P
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__u32 reserved3:6; //bit18, reserved
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__u32 SigmaEn:1; //bit24, sigma delta enbale
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__u32 reserved4:3; //bit25, reserved
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__u32 Lock:1; //bit28, pll is stable flag, 1-pll has stabled
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__u32 reserved5:2; //bit29, reserved
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__u32 PLLEn:1; //bit31, 0-disable, 1-enable, (24Mhz*N*K)/(M*P)
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} bits;
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}__ccmu_pll1_reg0000_t;
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typedef struct __CCMU_PLL2_REG0008
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{
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__u32 FactorM:5; //bit0, PLL2 prev division M
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__u32 reserved0:3; //bit5, reserved
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__u32 FactorN:7; //bit8, PLL2 factor N
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__u32 reserved1:1; //bit15, reserved
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__u32 FactorP:4; //bit16, PLL2 post division
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__u32 reserved2:4; //bit20, reserved
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__u32 SdmEn:1; //bit24, pll sdm enable, factorN only low 4 bits valid when enable
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__u32 reserved3:3; //bit25, reserved
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__u32 Lock:1; //bit28, pll stable flag
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__u32 reserved4:2; //bit29, reserved
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__u32 PLLEn:1; //bit31, PLL2 enable
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} __ccmu_pll2_reg0008_t;
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typedef struct __CCMU_MEDIA_PLL
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{
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__u32 FactorM:4; //bit0, PLL3 FactorM
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__u32 reserved0:4; //bit4, reserved
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__u32 FactorN:7; //bit8, PLL factor N
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__u32 reserved1:5; //bit15, reserved
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__u32 SdmEn:1; //bit20, sdm enable
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__u32 reserved2:3; //bit21, reserved
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__u32 ModeSel:1; //bit24, PLL mode select
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__u32 FracMod:1; //bit25, PLL out is 0:270Mhz, 1:297Mhz
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__u32 reserved3:2; //bit26, reserved
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__u32 Lock:1; //bit28, lock flag
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__u32 reserved4:1; //bit29, reserved
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__u32 CtlMode:1; //bit30, control mode, 0-controled by cpu, 1-control by DE
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__u32 PLLEn:1; //bit31, PLL3 enable
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} __ccmu_media_pll_t;
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typedef struct __CCMU_PLL5_REG0020
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{
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__u32 FactorM:2; //bit0, PLL5 factor M
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__u32 reserved0:6; //bit2, reserved
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__u32 FactorN:7; //bit8, PLL5 factor N
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__u32 Nmode:1; //bit15, Nmode
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__u32 reserved1:12; //bit16, reserved
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__u32 Lock:1; //bit28, lock flag
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__u32 reserved2:1; //bit29, reserved
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__u32 SDRPLL_UDP:1; //bit30,
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__u32 PLLEn:1; //bit31, PLL5 Enable
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} __ccmu_pll5_reg0020_t;
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typedef struct __CCMU_PLL6_REG0028
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{
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__u32 FactorM:2; //bit0, PLL6 factor M
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__u32 reserved0:2; //bit2, reserved
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__u32 FactorK:2; //bit4, PLL6 factor K
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__u32 reserved1:2; //bit6, reserved
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__u32 FactorN:5; //bit8, PLL6 factor N
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__u32 reserved2:3; //bit13, reserved
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__u32 Pll24MPdiv:2; //bit16, PLL 24M output clock post divider
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__u32 Pll24MOutEn:1; //bit18, PLL 24M output enable
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__u32 reserved3:5; //bit19, reserved
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__u32 PllClkOutEn:1; //bit24, pll clock output enable
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__u32 PLLBypass:1; //bit25, PLL6 output bypass enable
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__u32 reserved4:2; //bit26, reserved
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__u32 Lock:1; //bit28, lock flag
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__u32 reserved5:2; //bit29, reserved
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__u32 PLLEn:1; //bit31, PLL6 enable
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} __ccmu_pll6_reg0028_t;
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#define AC327_CLKSRC_LOSC (0)
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#define AC327_CLKSRC_HOSC (1)
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#define AC327_CLKSRC_PLL1 (2)
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typedef union{
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__u32 dwval;
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struct
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{
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__u32 AXIClkDiv:2; //bit0, AXI clock divide ratio, 000-1, 001-2, 010-3, 011-4
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__u32 reserved0:6; //bit2, reserved
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__u32 AtbApbClkDiv:2; //bit8, ATB/APB clock div, 00-1, 01-2, 1x-4
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__u32 reserved1:6; //bit10, reserved
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__u32 CpuClkSrc:2; //bit16, CPU1/2/3/4 clock source select, 00-internal LOSC, 01-HOSC, 10/11-PLL1
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__u32 reserved2:14; //bit18, reserved
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} bits;
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}__ccmu_sysclk_ratio_reg0050_t;
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#define AHB1_CLKSRC_LOSC (0)
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#define AHB1_CLKSRC_HOSC (1)
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#define AHB1_CLKSRC_AXI (2)
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#define AHB1_CLKSRC_PLL6 (3)
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typedef union{
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__u32 dwval;
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struct
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{
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__u32 reserved0:4; //bit0, reserved
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__u32 Ahb1Div:2; //bit4, ahb1 clock divide ratio,1/2/4/8
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__u32 Ahb1PreDiv:2; //bit6, ahb1 clock pre-divide ratio 1/2/3/4
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__u32 Apb1Div:2; //bit8, apb1 clock divide ratio 2/2/4/8, source is ahb1
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__u32 reserved1:2; //bit10, reserved
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__u32 Ahb1ClkSrc:2; //bit12, ahb1 clock source select, 00-LOSC, 01-OSC24M, 10-AXI, 11-PLL6/ahb1_pre_div
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__u32 reserved2:18; //bit26, reserved
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} bits;
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}__ccmu_ahb1_ratio_reg0054_t;
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#define APB2_CLKSRC_LOSC (0)
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#define APB2_CLKSRC_HOSC (1)
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#define APB2_CLKSRC_PLL24M (2)
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#define APB2_CLKSRC_PLL6 (3)
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typedef union{
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__u32 dwval;
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struct
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{
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__u32 DivM:5; //bit0, clock divide ratio m
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__u32 reserved:11; //bit5, reserved
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__u32 DivN:2; //bit16, clock pre-divide ratio 1/2/4/8
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__u32 reserved1:6; //bit18, reserved
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__u32 ClkSrc:2; //bit24, clock source select, 00-LOSC, 01-OSC24M, 10/11-PLL6
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__u32 reserved2:6; //bit26, reserved
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} bits;
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} __ccmu_apb2_ratio_reg0058_t;
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typedef struct __CCMU_PLLLOCK_REG0200
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{
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__u32 LockTime:16; //bit0, PLL lock time, based on us
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__u32 reserved:16; //bit16, reserved
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} __ccmu_plllock_reg0200_t;
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typedef struct __CCMU_REG_LIST
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{
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volatile __ccmu_pll1_reg0000_t Pll1Ctl; //0x0000, PLL1 control, cpux
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volatile __u32 reserved0; //0x0004, reserved
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volatile __ccmu_pll2_reg0008_t Pll2Ctl; //0x0008, PLL2 control, audio
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volatile __u32 reserved1; //0x000c, reserved
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volatile __u32 Pll3Ctl; //0x0010, PLL3 control, video
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volatile __u32 reserved2; //0x0014, reserved
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volatile __u32 reserved3; //0x0018, PLL4 control, ve
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volatile __u32 reserved4; //0x001c, reserved
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volatile __ccmu_pll5_reg0020_t Pll5Ctl; //0x0020, PLL5 control, ddr0 ctrl
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volatile __u32 reserved5; //0x0024, reserved
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volatile __ccmu_pll6_reg0028_t Pll6Ctl; //0x0028, PLL6 control, periph
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volatile __u32 reserved6; //0x002c, reserved
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volatile __u32 PllVideo1; //0x0030, reserved
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volatile __u32 Pll24M; //0x0034, reserved
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volatile __u32 reserved7; //0x0038, PLL8 control, gpu
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volatile __u32 reserved8; //0x003c, reserved
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volatile __u32 reserved9; //0x0040, MIPI PLL control
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volatile __u32 Pll9Ctl; //0x0044, PLL9 control, hsic?
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volatile __u32 Pll10Ctl; //0x0048, PLL10 control,de
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volatile __u32 PllDdr1Ctl; //0x004c, pll ddr1 ctrl reg
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volatile __ccmu_sysclk_ratio_reg0050_t SysClkDiv; //0x0050, system clock divide ratio
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volatile __ccmu_ahb1_ratio_reg0054_t Ahb1Div; //0x0054, ahb1/apb1 clock divide ratio
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volatile __ccmu_apb2_ratio_reg0058_t Apb2Div; //0x0058, apb2 clock divide ratio
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volatile __u32 reserved51; //0x005c, reserved
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volatile __u32 AhbGate0; //0x0060, bus gating reg0
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volatile __u32 AhbGate1; //0x0064, bus gating reg1
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volatile __u32 Apb1Gate; //0x0068, bus gating reg2
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volatile __u32 Apb2Gate0; //0x006c, bus gating reg3
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volatile __u32 Apb2Gate1; //0x0070, bus gating reg4
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volatile __u32 reserved71; //0x0074, bus gating reg4
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volatile __u32 Gpadc; //0x0078, bus gating reg4
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volatile __u32 Ths; //0x007C, bus gating reg4
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volatile __u32 Nand0; //0x0080, nand controller 0 clock
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volatile __u32 reserved81; //0x0084, reserved
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volatile __u32 Sd0; //0x0088, sd/mmc controller 0 clock
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volatile __u32 Sd1; //0x008c, sd/mmc controller 1 clock
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volatile __u32 Sd2; //0x0090, sd/mmc controller 2 clock
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volatile __u32 Sd3; //0x0094, reserved
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volatile __u32 reserved91[2]; //0x0098, reserved
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volatile __u32 Spi0; //0x00a0, spi controller 0 clock
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volatile __u32 Spi1; //0x00a4, spi controller 1 clock
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volatile __u32 Spi2; //0x00a8, reserved
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volatile __u32 reserved101; //0x00ac, reserved
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volatile __u32 I2s0; //0x00b0, daudio-0 clock?
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volatile __u32 I2s1; //0x00b4, daudio-1 clock?
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volatile __u32 reserved102[2]; //0x00b8, reserved
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volatile __u32 SpdifClk; //0x00c0, reserved
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volatile __u32 dsd; //0x00c4, reserved
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volatile __u32 dmic; //0x00c8, reserved
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volatile __u32 Usb; //0x00cc, usb phy clock
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volatile __u32 reserved111; //0x00d0, reserved
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volatile __u32 reserved12[7]; //0x00d4, reserved
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volatile __u32 PllDdrAuxiliary; //0x00f0, reserved
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volatile __u32 DramCfg; //0x00f4, dram configuration clock
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volatile __u32 PllDdrCfg; //0x00f8, pll ddr config reg
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volatile __u32 MbusResetReg; //0x00fc, mbus reset reg
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volatile __u32 DramGate; //0x0100, dram module clock
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volatile __u32 De0; //0x0104, BE0 module clock
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volatile __u32 Ee0; //0x0108, reserved
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volatile __u32 Edma; //0x010c, FE0 module clock
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volatile __u32 reserved132; //0x0110, reserved
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volatile __u32 reserved133; //0x0114, reserved
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volatile __u32 Lcd0Ch0; //0x0118, LCD0 CH0 module clock
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volatile __u32 reserved134; //0x011c, reserved
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volatile __u32 reserved14[4]; //0x0120, reserved
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volatile __u32 CsiMisc; //0x0130, reserved
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volatile __u32 Csi0; //0x0134, csi0 module clock
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volatile __u32 reserved142[2]; //0x0138, reserved
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volatile __u32 Adda; //0x0140, adda digital clock register
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volatile __u32 reserved143; //0x0144, avs module clock
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volatile __u32 Wlan; //0x0148, reserved
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volatile __u32 reserved15; //0x014c, reserved
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volatile __u32 reserved151; //0x0150, reserved
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volatile __u32 reserved152; //0x0154, reserved
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volatile __u32 reserved153; //0x0158, reserved
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volatile __u32 MBus0; //0x015C, MBUS controller 0 clock
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volatile __u32 reserved160[40]; //0x0160, reserved
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volatile __ccmu_plllock_reg0200_t PllLock; //0x0200, pll lock time
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volatile __u32 Pll1Lock; //0x0204, pll1 cpu lock time
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volatile __u32 reserved200[5]; //0x0208-0x21c, reserved
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volatile __u32 Pll24mBias; //0x21c, pll cpux bias reg
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volatile __u32 PllxBias[1]; //0x220, pll cpux bias reg
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volatile __u32 PllAudioBias; //0x224, pll audio bias reg
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volatile __u32 PllVideo0Bias; //0x228, pll vedio bias reg
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volatile __u32 reserved201; //0x22c, pll ve bias reg
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volatile __u32 PllDram0Bias; //0x230, pll dram0 bias reg
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volatile __u32 PllPeriphBias; //0x234, pll periph bias reg
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volatile __u32 PllVideo1Bias; //0x238, reserved
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volatile __u32 reserved202[2]; //0x23c, pll gpu bias reg
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volatile __u32 PllPeriph1Bias; //0x244, pll hsic bias reg
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volatile __u32 PllDeBias; //0x248, pll de bias reg
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volatile __u32 PllDram1BiasReg; //0x24c, pll dram1 bias
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volatile __u32 Pll1Tun; //0x250, pll1 tun reg
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volatile __u32 reserved203[3]; //0x254-0x25c, reserved
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volatile __u32 Pll5Tun; //0x260, pll5 tun reg
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volatile __u32 reserved204[7]; //0x264-0x26c, reserved
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volatile __u32 Pll1Pattern; //0x280, pll cpux pattern reg
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volatile __u32 PllAudioPattern; //0x284, pll audio pattern reg
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volatile __u32 PllVedio0Pattern; //0x288, pll vedio pattern reg
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volatile __u32 reserved205[4]; //0x28c, pll ve pattern reg
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volatile __u32 PllVedio1Pattern; //0x298, reserved
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volatile __u32 reserved206[2]; //0x29c, pll gpu pattern reg
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volatile __u32 PllPeriph1Pattern; //0x2a4, pll hsic pattern reg
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volatile __u32 PllDePattern; //0x2a8, pll de pattern reg
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volatile __u32 PllDram0PatternReg0; //0x2ac, pll dram1 pattern reg0
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volatile __u32 PllDram0PatternReg1; //0x2b0, pll dram1 pattern reg1
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volatile __u32 PllDram1PatternReg0; //0x2b4, pll dram1 pattern reg0
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volatile __u32 PllDram1PatternReg1; //0x2b8, pll dram1 pattern reg1
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volatile __u32 reserved207; //0x2bc, reserved
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volatile __u32 AhbReset0; //0x02c0, AHB1 module reset register 0
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volatile __u32 AhbReset1; //0x02c4, AHB1 module reset register 1
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volatile __u32 reserved208[2]; //0x02c8 0x02cc, AHB1 module reset register 1
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volatile __u32 Apb1Reset; //0x02d0, APB1 module reset register
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volatile __u32 reserved22; //0x02d4, reserved
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volatile __u32 Apb2Reset; //0x02d8, APB2 module reset register
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} __ccmu_reg_list_t;
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#endif // #ifndef __MEM_CCMU_SUN50W1P1_H__
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