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OSHW-DEIMOS/SOFTWARE/A64-TERES/linux-a64/drivers/pinctrl/sunxi/pinctrl-sun8iw10p1.c
Dimitar Gamishev f9b0e7a283 linux
2017-10-13 14:07:04 +03:00

693 lines
24 KiB
C
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/*
* Allwinner A23 SoCs pinctrl driver.
*
* Copyright (C) 2014 Jackie Hwang
*
* Jackie Hwang <huangshr@allwinnertech.com>
*
* Copyright (C) 2014 Chen-Yu Tsai
*
* Chen-Yu Tsai <wens@csie.org>
*
* Copyright (C) 2014 Maxime Ripard
*
* Maxime Ripard <maxime.ripard@free-electrons.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-sunxi.h"
static const struct sunxi_desc_pin sun8iw10p1_pins[] = {
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"),
SUNXI_FUNCTION(0x3, "jtag0"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"),
SUNXI_FUNCTION(0x3, "jtag0"),
SUNXI_FUNCTION(0x4, "spdif0"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"),
SUNXI_FUNCTION(0x3, "jtag0"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"),
SUNXI_FUNCTION(0x3, "jtag0"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart0"),
SUNXI_FUNCTION(0x3, "pwm0"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart0"),
SUNXI_FUNCTION(0x3, "pwm1"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "twi0"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "twi0"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)),
#if defined(CONFIG_FPGA_V4_PLATFORM)
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"),
SUNXI_FUNCTION(0x3, "uart4"),
SUNXI_FUNCTION(0x4, "uart0"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"),
SUNXI_FUNCTION(0x3, "uart4"),
SUNXI_FUNCTION(0x4, "uart0"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)),
#else
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"),
SUNXI_FUNCTION(0x3, "uart4"),
SUNXI_FUNCTION(0x4, "twi1"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"),
SUNXI_FUNCTION(0x3, "uart4"),
SUNXI_FUNCTION(0x4, "twi1"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)),
#endif
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"),
SUNXI_FUNCTION(0x3, "uart4"),
SUNXI_FUNCTION(0x4, "pwm2"),
SUNXI_FUNCTION(0x5, "wifi_uart0"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"),
SUNXI_FUNCTION(0x3, "uart4"),
SUNXI_FUNCTION(0x4, "pwm3"),
SUNXI_FUNCTION(0x5, "wifi_uart0"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s1"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s1"),
SUNXI_FUNCTION(0x4, "pwm4"),
SUNXI_FUNCTION(0x5, "uart3"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s1"),
SUNXI_FUNCTION(0x4, "pwm5"),
SUNXI_FUNCTION(0x5, "uart3"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s1"),
SUNXI_FUNCTION(0x3, "ac0"),
SUNXI_FUNCTION(0x4, "twi1"),
SUNXI_FUNCTION(0x5, "uart3"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s1"),
SUNXI_FUNCTION(0x3, "ac0"),
SUNXI_FUNCTION(0x4, "twi1"),
SUNXI_FUNCTION(0x5, "uart3"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)),
/*Hole*/
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"),
SUNXI_FUNCTION(0x4, "spi0"),
SUNXI_FUNCTION(0x7, "io_disabled")),
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"),
SUNXI_FUNCTION(0x3, "sdc2"),
SUNXI_FUNCTION(0x4, "spi0"),
SUNXI_FUNCTION(0x5, "sdc3"),
SUNXI_FUNCTION(0x7, "io_disabled")),
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"),
SUNXI_FUNCTION(0x4, "spi0"),
SUNXI_FUNCTION(0x7, "io_disabled")),
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"),
SUNXI_FUNCTION(0x4, "spi0"),
SUNXI_FUNCTION(0x7, "io_disabled")),
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"),
SUNXI_FUNCTION(0x3, "sdc2"),
SUNXI_FUNCTION(0x5, "sdc3"),
SUNXI_FUNCTION(0x7, "io_disabled")),
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"),
SUNXI_FUNCTION(0x3, "sdc2"),
SUNXI_FUNCTION(0x5, "sdc3"),
SUNXI_FUNCTION(0x7, "io_disabled")),
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"),
SUNXI_FUNCTION(0x3, "sdc2"),
SUNXI_FUNCTION(0x4, "uart1"),
SUNXI_FUNCTION(0x5, "sdc3"),
SUNXI_FUNCTION(0x7, "io_disabled")),
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"),
SUNXI_FUNCTION(0x3, "sdc2"),
SUNXI_FUNCTION(0x4, "uart1"),
SUNXI_FUNCTION(0x5, "sdc3"),
SUNXI_FUNCTION(0x7, "io_disabled")),
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"),
SUNXI_FUNCTION(0x3, "sdc2"),
SUNXI_FUNCTION(0x4, "uart1"),
SUNXI_FUNCTION(0x5, "sdc3"),
SUNXI_FUNCTION(0x7, "io_disabled")),
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"),
SUNXI_FUNCTION(0x3, "sdc2"),
SUNXI_FUNCTION(0x4, "uart1"),
SUNXI_FUNCTION(0x5, "sdc3"),
SUNXI_FUNCTION(0x7, "io_disabled")),
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"),
SUNXI_FUNCTION(0x3, "sdc2"),
SUNXI_FUNCTION(0x4, "uart1"),
SUNXI_FUNCTION(0x5, "sdc3"),
SUNXI_FUNCTION(0x7, "io_disabled")),
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"),
SUNXI_FUNCTION(0x3, "sdc2"),
SUNXI_FUNCTION(0x4, "uart1"),
SUNXI_FUNCTION(0x5, "sdc3"),
SUNXI_FUNCTION(0x7, "io_disabled")),
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"),
SUNXI_FUNCTION(0x3, "sdc2"),
SUNXI_FUNCTION(0x4, "uart1"),
SUNXI_FUNCTION(0x5, "sdc3"),
SUNXI_FUNCTION(0x7, "io_disabled")),
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"),
SUNXI_FUNCTION(0x3, "sdc2"),
SUNXI_FUNCTION(0x4, "uart1"),
SUNXI_FUNCTION(0x5, "sdc3"),
SUNXI_FUNCTION(0x7, "io_disabled")),
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"),
SUNXI_FUNCTION(0x3, "sdc2"),
SUNXI_FUNCTION(0x5, "sdc3"),
SUNXI_FUNCTION(0x7, "io_disabled")),
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"),
SUNXI_FUNCTION(0x3, "uart1"),
SUNXI_FUNCTION(0x4, "csi0"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"),
SUNXI_FUNCTION(0x3, "uart1"),
SUNXI_FUNCTION(0x4, "csi0"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"),
SUNXI_FUNCTION(0x3, "uart5"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"),
SUNXI_FUNCTION(0x3, "uart5"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"),
SUNXI_FUNCTION(0x3, "uart5"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"),
SUNXI_FUNCTION(0x3, "uart5"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"),
SUNXI_FUNCTION(0x3, "uart1"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"),
SUNXI_FUNCTION(0x3, "uart1"),
SUNXI_FUNCTION(0x4, "csi0"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"),
SUNXI_FUNCTION(0x4, "csi0"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 13)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"),
SUNXI_FUNCTION(0x4, "csi0"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 14)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"),
SUNXI_FUNCTION(0x4, "csi0"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 15)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"),
SUNXI_FUNCTION(0x4, "csi0"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 16)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"),
SUNXI_FUNCTION(0x4, "csi0"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 17)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"),
SUNXI_FUNCTION(0x4, "csi0"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 18)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"),
SUNXI_FUNCTION(0x4, "csi0"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 19)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"),
SUNXI_FUNCTION(0x4, "csi0"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 20)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"),
SUNXI_FUNCTION(0x4, "csi0"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 21)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"),
SUNXI_FUNCTION(0x4, "csi0"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 22)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"),
SUNXI_FUNCTION(0x4, "csi0"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 23)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"),
SUNXI_FUNCTION(0x3, "spi2"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 24)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"),
SUNXI_FUNCTION(0x3, "spi2"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 25)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"),
SUNXI_FUNCTION(0x3, "spi2"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 26)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"),
SUNXI_FUNCTION(0x3, "spi2"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 27)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 28),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "pwm0"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 28)),
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "sdc0"),
SUNXI_FUNCTION(0x4, "jtag0"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "sdc0"),
SUNXI_FUNCTION(0x4, "jtag0"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "sdc0"),
SUNXI_FUNCTION(0x4, "uart0"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "sdc0"),
SUNXI_FUNCTION(0x4, "jtag0"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "sdc0"),
SUNXI_FUNCTION(0x4, "uart0"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "sdc0"),
SUNXI_FUNCTION(0x4, "jtag0"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)),
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "pwm6"),
SUNXI_FUNCTION(0x3, "dmic0"),
SUNXI_FUNCTION(0x4, "spi1"),
SUNXI_FUNCTION(0x5, "sdc1"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 0)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "pwm7"),
SUNXI_FUNCTION(0x3, "dmic0"),
SUNXI_FUNCTION(0x4, "spi1"),
SUNXI_FUNCTION(0x5, "sdc1"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 1)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "twi1"),
SUNXI_FUNCTION(0x3, "dmic0"),
SUNXI_FUNCTION(0x4, "spi1"),
SUNXI_FUNCTION(0x5, "sdc1"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 2)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "twi1"),
SUNXI_FUNCTION(0x3, "dmic0"),
SUNXI_FUNCTION(0x4, "spi1"),
SUNXI_FUNCTION(0x5, "sdc1"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 1)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "twi2"),
SUNXI_FUNCTION(0x3, "dmic0"),
SUNXI_FUNCTION(0x4, "spi1"),
SUNXI_FUNCTION(0x5, "sdc1"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 4)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "twi2"),
SUNXI_FUNCTION(0x4, "ac0"),
SUNXI_FUNCTION(0x5, "sdc1"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 5)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s0"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 6)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s0"),
SUNXI_FUNCTION(0x3, "dsd0"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 7)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s0"),
SUNXI_FUNCTION(0x3, "dsd0"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 8)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s0"),
SUNXI_FUNCTION(0x3, "dsd0"),
SUNXI_FUNCTION(0x4, "bist_result0"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 9)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2s0"),
SUNXI_FUNCTION(0x3, "dsd0"),
SUNXI_FUNCTION(0x4, "bist_result1"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 10)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spdif0"),
SUNXI_FUNCTION(0x4, "pll_lock_dbg"),
SUNXI_FUNCTION(0x7, "io_disabled"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 11)),
/* Hole */
#if defined(CONFIG_FPGA_V4_PLATFORM)
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x7, "io_disabled")),
#endif
};
static const struct sunxi_pinctrl_desc sun8iw10p1_pinctrl_data = {
.pins = sun8iw10p1_pins,
.npins = ARRAY_SIZE(sun8iw10p1_pins),
.pin_base = 0,
.irq_banks = 4,
};
static int sun8iw10p1_pinctrl_probe(struct platform_device *pdev)
{
return sunxi_pinctrl_init(pdev,
&sun8iw10p1_pinctrl_data);
}
static struct of_device_id sun8iw10p1_pinctrl_match[] = {
{ .compatible = "allwinner,sun8iw10p1-pinctrl", },
{}
};
MODULE_DEVICE_TABLE(of, sun8iw10p1_pinctrl_match);
static struct platform_driver sun8iw10p1_pinctrl_driver = {
.probe = sun8iw10p1_pinctrl_probe,
.driver = {
.name = "sun8iw10p1-pinctrl",
.owner = THIS_MODULE,
.of_match_table = sun8iw10p1_pinctrl_match,
},
};
static int __init sun8iw10p1_pio_init(void)
{
int ret;
ret = platform_driver_register(&sun8iw10p1_pinctrl_driver);
if (IS_ERR_VALUE(ret)) {
pr_debug("register sun8iw10p1 pio controller failed\n");
return -EINVAL;
}
return 0;
}
postcore_initcall(sun8iw10p1_pio_init);
MODULE_AUTHOR("Jackie Hwang <huangshr@allwinnertech.com>");
MODULE_AUTHOR("Chen-Yu Tsai <wens@csie.org>");
MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com");
MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com");
MODULE_DESCRIPTION("Allwinner A23 R_PIO pinctrl driver");
MODULE_LICENSE("GPL");
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