171 lines
4.0 KiB
C
Executable File
171 lines
4.0 KiB
C
Executable File
/*
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* Copyright (c) 2009 jokeliu@163.com
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* Author : jokeliujl <jokeliu@163.com>
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* Date : 2010-10-01
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*/
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/* qf9700 spec. register table */
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/* Registers */
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#define NCR 0x00
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#define NSR 0x01
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#define TCR 0x02
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#define TSR1 0x03
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#define TSR2 0x04
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#define RCR 0x05
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#define RSR 0x06
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#define ROCR 0x07
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#define BPTR 0x08
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#define FCTR 0x09
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#define FCR 0x0A
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#define EPCR 0x0B
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#define EPAR 0x0C
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#define EPDR 0x0D /* 0x0D ~ 0x0E */
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#define WCR 0x0F
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#define PAR 0x10
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#define MAR 0x16
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#define PRR 0x1F
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#define TWPAL 0x20
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#define TWPAH 0x21
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#define TRPAL 0x22
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#define TRPAH 0x23
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#define RWPAL 0x24
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#define RWPAH 0x25
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#define RRPAL 0x26
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#define RRPAH 0x27
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#define VID 0x28
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#define PID 0x2A
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#define CHIPR 0x2C
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#define USBDA 0xF0
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#define RXC 0xF1
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#define TXC_USBS 0xF2
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#define USBC 0xF4
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/* Bit definition for registers */
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/* Network Control Reg */
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#define NCR_RST (1 << 0)
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#define NCR_LBK (3 << 1)
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#define NCR_FDX (1 << 3)
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#define NCR_WAKEEN (1 << 6)
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/* Network Status Reg */
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#define NQF_RXRDY (1 << 0)
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#define NQF_RXOV (1 << 1)
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#define NQF_TX1END (1 << 2)
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#define NQF_TX2END (1 << 3)
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#define NQF_TXFULL (1 << 4)
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#define NQF_WAKEST (1 << 5)
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#define NQF_LINKST (1 << 6)
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#define NQF_SPEED (1 << 7)
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/* Tx Control Reg */
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#define TCR_CRC_DIS (1 << 1)
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#define TCR_PAD_DIS (1 << 2)
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#define TCR_LC_CARE (1 << 3)
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#define TCR_CRS_CARE (1 << 4)
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#define TCR_EXCECM (1 << 5)
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#define TCR_LF_EN (1 << 6)
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/* Tx Status Reg for Packet 1 */
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#define TSR1_EC (1 << 2)
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#define TSR1_COL (1 << 3)
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#define TSR1_LC (1 << 4)
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#define TSR1_NC (1 << 5)
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#define TSR1_LOC (1 << 6)
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#define TSR1_TLF (1 << 7)
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/* Tx Status Reg for Packet 2 */
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#define TSR2_EC (1 << 2)
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#define TSR2_COL (1 << 3)
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#define TSR2_LC (1 << 4)
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#define TSR2_NC (1 << 5)
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#define TSR2_LOC (1 << 6)
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#define TSR2_TLF (1 << 7)
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/* Rx Control Reg */
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#define RCR_RXEN (1 << 0)
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#define RCR_PRMSC (1 << 1)
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#define RCR_RUNT (1 << 2)
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#define RCR_ALL (1 << 3)
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#define RCR_DIS_CRC (1 << 4)
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#define RCR_DIS_LONG (1 << 5)
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/* Rx Status Reg */
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#define RQF_AE (1 << 2)
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#define RQF_MF (1 << 6)
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#define RQF_RF (1 << 7)
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/* Recv Overflow Counter Reg */
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#define ROCR_ROC (0x7F << 0)
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#define ROCR_RXFU (1 << 7)
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/* Back Pressure Threshold Reg */
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#define BPTR_JPT (0x0F << 0)
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#define BPTR_BPHW (0x0F << 4)
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/* Flow Control Threshold Reg */
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#define FCTR_LWOT (0x0F << 0)
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#define FCTR_HWOT (0x0F << 4)
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/* rx/tx Flow Control Reg */
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#define FCR_FLCE (1 << 0)
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#define FCR_BKPA (1 << 4)
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#define FCR_TXPEN (1 << 5)
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#define FCR_TXPF (1 << 6)
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#define FCR_TXP0 (1 << 7)
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/* EEPROM & PHY Control Reg */
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#define EPCR_ERRE (1 << 0)
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#define EPCR_ERPRW (1 << 1)
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#define EPCR_ERPRR (1 << 2)
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#define EPCR_EPOS (1 << 3)
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#define EPCR_WEP (1 << 4)
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/* EEPROM & PHY Address Reg */
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#define EPAR_EROA (0x3F << 0)
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#define EPAR_PHY_ADR (0x03 << 6)
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/* Wakeup Control Reg */
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#define WCR_MAGICST (1 << 0)
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#define WCR_LINKST (1 << 2)
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#define WCR_MAGICEN (1 << 3)
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#define WCR_LINKEN (1 << 5)
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/* Phy Reset Reg */
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#define PRR_PHY_RST (1 << 0)
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/* USB Device Address Reg */
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#define USBDA_USBFA (0x7F << 0)
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/* TX packet Counter & USB Status Reg */
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#define TXC_USBS_TXC0 (1 << 0)
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#define TXC_USBS_TXC1 (1 << 1)
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#define TXC_USBS_TXC2 (1 << 2)
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#define TXC_USBS_EP1RDY (1 << 5)
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#define TXC_USBS_SUSFLAG (1 << 6)
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#define TXC_USBS_RXFAULT (1 << 7)
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/* USB Control Reg */
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#define USBC_EP3NAK (1 << 4)
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#define USBC_EP3ACK (1 << 5)
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/* Variables */
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#define QF_RD_REGS 0x00
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#define QF_WR_REGS 0x01
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#define QF_WR_REG 0x03
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#define QF_REQ_RD_REG (USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE)
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#define QF_REQ_WR_REG (USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE)
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#define QF_SHARE_TIMEOUT 1000
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#define QF_EEPROM_LEN 256
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#define QF_MCAST_SIZE 8
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#define QF_MCAST_MAX 64
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#define QF_TX_OVERHEAD 2 // 2bytes header
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#define QF_RX_OVERHEAD 7 // 3bytes header + 4crc tail
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/*----------------------------------------------------------------------------------------------*/
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