135 lines
4.4 KiB
C
135 lines
4.4 KiB
C
#ifndef __DPCD_EDID_H
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#define __DPCD_EDID_H
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#include "../video/edid.h"
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#define DPCD_REV 0x00
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#define DPCD_MAX_LINK_RATE 0x01
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#define DPCD_MAX_LANE_CNT 0x02
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#define DPCD_MAX_DOWNSPREAD 0x03
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#define DPCD_NORP 0x04
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#define DPCD_DOWNSTREAMPORT_PRESENT 0x05
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#define DPCD_RECEIVE_PORT0_CAP_0 0x08
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#define DPCD_RECEIVE_PORT0_CAP_1 0x09
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#define DPCD_RECEIVE_PORT0_CAP_2 0x0a
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#define DPCD_RECEIVE_PORT0_CAP_3 0x0b
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#define DPCD_LINK_BW_SET 0x100
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#define DPCD_LANE_CNT_SET 0x101
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#define DPCD_TRAINING_PATTERN_SET 0x102
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#define DPCD_TRAINING_LANE0_SET 0x103
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#define DPCD_TRAINING_LANE1_SET 0x104
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#define DPCD_TRAINING_LANE2_SET 0x105
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#define DPCD_TRAINING_LANE3_SET 0x106
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#define DPCD_DOWNSPREAD_CTRL 0x107
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#define DPCD_SINK_COUNT 0x200
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#define DPCD_DEVICE_SERVICE_IRQ_VECTOR 0x201
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#define DPCD_LANE0_1_STATUS 0x202
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#define DPCD_LANE2_3_STATUS 0x203
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#define DPCD_LANE_ALIGN_STATUS_UPDATED 0x204
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#define DPCD_SINK_STATUS 0x205
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#define DPCD_ADJUST_REQUEST_LANE0_1 0x206
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#define DPCD_ADJUST_REQUEST_LANE2_3 0x207
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#define DPCD_TRAINING_SCORE_LANE0 0x208
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#define DPCD_TRAINING_SCORE_LANE1 0x209
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#define DPCD_TRAINING_SCORE_LANE2 0x20a
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#define DPCD_TRAINING_SCORE_LANE3 0x20b
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#define DPCD_SINK_POWER_STATE 0x0600
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/* DPCD_ADDR_MAX_LANE_COUNT */
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#define DPCD_ENHANCED_FRAME_CAP(x) (((x) >> 7) & 0x1)
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#define DPCD_MAX_LANE_COUNT(x) ((x) & 0x1f)
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/* DPCD_ADDR_LANE_COUNT_SET */
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#define DPCD_ENHANCED_FRAME_EN (0x1 << 7)
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#define DPCD_LANE_COUNT_SET(x) ((x) & 0x1f)
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/* DPCD_ADDR_TRAINING_PATTERN_SET */
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#define DPCD_SCRAMBLING_DISABLED (0x1 << 5)
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#define DPCD_SCRAMBLING_ENABLED (0x0 << 5)
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#define DPCD_TRAINING_PATTERN_2 (0x2 << 0)
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#define DPCD_TRAINING_PATTERN_1 (0x1 << 0)
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#define DPCD_TRAINING_PATTERN_DISABLED (0x0 << 0)
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/* DPCD_ADDR_TRAINING_LANE0_SET */
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#define DPCD_MAX_PRE_EMPHASIS_REACHED (0x1 << 5)
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#define DPCD_PRE_EMPHASIS_SET(x) (((x) & 0x3) << 3)
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#define DPCD_PRE_EMPHASIS_GET(x) (((x) >> 3) & 0x3)
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#define DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0 (0x0 << 3)
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#define DPCD_MAX_SWING_REACHED (0x1 << 2)
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#define DPCD_VOLTAGE_SWING_SET(x) (((x) & 0x3) << 0)
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#define DPCD_VOLTAGE_SWING_GET(x) (((x) >> 0) & 0x3)
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#define DPCD_VOLTAGE_SWING_PATTERN1_LEVEL0 (0x0 << 0)
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/* DPCD_ADDR_LANE0_1_STATUS */
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#define DPCD_LANE_SYMBOL_LOCKED (0x1 << 2)
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#define DPCD_LANE_CHANNEL_EQ_DONE (0x1 << 1)
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#define DPCD_LANE_CR_DONE (0x1 << 0)
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#define DPCD_CHANNEL_EQ_BITS (DPCD_LANE_CR_DONE| \
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DPCD_LANE_CHANNEL_EQ_DONE|\
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DPCD_LANE_SYMBOL_LOCKED)
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#define DPCD_TEST_REQUEST 0x218
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#define DPCD_TEST_LINK_RATE 0x219
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#define DPCD_TEST_LANE_COUNT 0x220
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#define DPCD_TEST_RESPONSE 0x260
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#define DPCD_TEST_EDID_CHECKSUM 0x261
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#define TEST_ACK 0x01
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#define DPCD_TEST_EDID_Checksum_Write 0x04//bit position
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#define DPCD_TEST_EDID_Checksum 0x261
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#define DPCD_SPECIFIC_INTERRUPT 0x10
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#define DPCD_USER_COMM1 0x22//define for downstream HDMI Rx sense detection
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#define AUX_ADDR_7_0(x) (((x) >> 0) & 0xff)
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#define AUX_ADDR_15_8(x) (((x) >> 8) & 0xff)
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#define AUX_ADDR_19_16(x) (((x) >> 16) & 0x0f)
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#define AUX_RX_COMM_I2C_DEFER (0x2 << 2)
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#define AUX_RX_COMM_AUX_DEFER (0x2 << 0)
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/* DPCD_ADDR_LANE_ALIGN__STATUS_UPDATED */
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#define DPCD_LINK_STATUS_UPDATED (0x1 << 7)
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#define DPCD_DOWNSTREAM_PORT_STATUS_CHANGED (0x1 << 6)
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#define DPCD_INTERLANE_ALIGN_DONE (0x1 << 0)
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/* DPCD_ADDR_TEST_REQUEST */
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#define DPCD_TEST_EDID_READ (0x1 << 2)
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/* DPCD_ADDR_TEST_RESPONSE */
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#define DPCD_TEST_EDID_CHECKSUM_WRITE (0x1 << 2)
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/* DPCD_ADDR_SINK_POWER_STATE */
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#define DPCD_SET_POWER_STATE_D0 (0x1 << 0)
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#define DPCD_SET_POWER_STATE_D4 (0x2 << 0)
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/*
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* EDID device address is 0x50.
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* However, if necessary, you must have set upper address
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* into E-EDID in I2C device, 0x30.
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*/
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#define EDID_ADDR 0x50
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#define E_EDID_ADDR 0x30
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#define EDID_EXTENSION_FLAG 0x7e
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#define EDID_CHECKSUM 0x7f
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static unsigned char inline edp_calc_edid_check_sum(unsigned char *edid_data)
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{
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int i;
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unsigned char sum = 0;
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for (i = 0; i < EDID_LENGTH; i++)
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sum = sum + edid_data[i];
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return sum;
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}
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#endif
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