113 lines
3.8 KiB
C
113 lines
3.8 KiB
C
#ifndef _DP_ANX9805_H_
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#define _DP_ANX9805_H_
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/**************register define for anx9805 anx9804********/
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#define DP_TX_VND_IDL_REG 0x00
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#define DP_TX_VND_IDH_REG 0x01
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#define DP_TX_DEV_IDL_REG 0x02
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#define DP_TX_DEV_IDH_REG 0x03
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#define DP_POWERD_CTRL_REG 0x05
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#define DP_TX_VID_CTRL1_REG 0x08
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#define DP_TX_VID_CTRL1_VID_EN 0x80 // bit position
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#define DP_POWERD_TOTAL_REG 0x02// bit position
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#define DP_POWERD_AUDIO_REG 0x10// bit position
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#define DP_TX_RST_CTRL_REG 0x06
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#define DP_TX_RST_CTRL2_REG 0x07
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#define DP_TX_RST_HW_RST 0x01 // bit position
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#define DP_TX_AUX_RST 0x04//bit position
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#define DP_TX_RST_SW_RST 0x02 // bit position
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#define DP_TX_PLL_CTRL_REG 0xC7
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#define DP_TX_EXTRA_ADDR_REG 0xCE
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#define DP_TX_PLL_FILTER_CTRL3 0xE1
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#define DP_TX_PLL_CTRL3 0xE6
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#define DP_TX_AC_MODE 0x40//bit position
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#define ANALOG_DEBUG_REG1 0xDC
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#define ANALOG_DEBUG_REG3 0xDE
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#define DP_TX_PLL_FILTER_CTRL1 0xDF
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#define DP_TX_PLL_FILTER_CTRL3 0xE1
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#define DP_TX_PLL_FILTER_CTRL 0xE2
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#define DP_TX_LINK_DEBUG_REG 0xB8
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#define DP_TX_GNS_CTRL_REG 0xCD
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#define DP_TX_AUX_CTRL_REG2 0xE9
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#define DP_TX_BUF_DATA_COUNT_REG 0xE4
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#define DP_TX_AUX_CTRL_REG 0xE5
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#define DP_TX_AUX_ADDR_7_0_REG 0xE6
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#define DP_TX_AUX_ADDR_15_8_REG 0xE7
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#define DP_TX_AUX_ADDR_19_16_REG 0xE8
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#define DP_TX_BUF_DATA_0_REG 0xf0
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#define DP_TX_SYS_CTRL4_REG 0x83
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#define DP_TX_SYS_CTRL4_ENHANCED 0x08//bit position
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#define DP_TX_LINK_BW_SET_REG 0xA0
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#define DP_TX_LANE_COUNT_SET_REG 0xA1
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#define DP_TX_LINK_TRAINING_CTRL_REG 0xA8
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#define DP_TX_LINK_TRAINING_CTRL_EN 0x01// bit position
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#define DP_TX_TRAINING_LANE0_SET_REG 0xA3
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#define DP_TX_TRAINING_LANE1_SET_REG 0xA4
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#define DP_TX_TRAINING_LANE2_SET_REG 0xA5
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#define DP_TX_TRAINING_LANE3_SET_REG 0xA6
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#define DP_TX_SYS_CTRL1_REG 0x80
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#define DP_TX_SYS_CTRL1_DET_STA 0x04// bit position
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#define DP_TX_SYS_CTRL2_REG 0x81
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#define DP_TX_SYS_CTRL3_REG 0x82
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#define DP_TX_SYS_CTRL2_CHA_STA 0x04// bit position
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#define DP_TX_VID_CTRL2_REG 0x09
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#define DP_TX_TOTAL_LINEL_REG 0x12
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#define DP_TX_TOTAL_LINEH_REG 0x13
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#define DP_TX_ACT_LINEL_REG 0x14
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#define DP_TX_ACT_LINEH_REG 0x15
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#define DP_TX_VF_PORCH_REG 0x16
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#define DP_TX_VSYNC_CFG_REG 0x17
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#define DP_TX_VB_PORCH_REG 0x18
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#define DP_TX_TOTAL_PIXELL_REG 0x19
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#define DP_TX_TOTAL_PIXELH_REG 0x1A
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#define DP_TX_ACT_PIXELL_REG 0x1B
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#define DP_TX_ACT_PIXELH_REG 0x1C
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#define DP_TX_HF_PORCHL_REG 0x1D
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#define DP_TX_HF_PORCHH_REG 0x1E
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#define DP_TX_HSYNC_CFGL_REG 0x1F
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#define DP_TX_HSYNC_CFGH_REG 0x20
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#define DP_TX_HB_PORCHL_REG 0x21
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#define DP_TX_HB_PORCHH_REG 0x22
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#define DP_TX_VID_CTRL10_REG 0x11
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#define DP_TX_VID_CTRL4_REG 0x0B
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#define DP_TX_VID_CTRL4_E_SYNC_EN 0x80//bit position
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#define DP_TX_VID_CTRL10_I_SCAN 0x04// bit position
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#define DP_TX_VID_CTRL10_VSYNC_POL 0x02// bit position
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#define DP_TX_VID_CTRL10_HSYNC_POL 0x01// bit position
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#define DP_TX_VID_CTRL4_BIST_WIDTH 0x04// bit position
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#define DP_TX_VID_CTRL4_BIST 0x08// bit position
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typedef enum
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{
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COLOR_6,
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COLOR_8,
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COLOR_10,
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COLOR_12
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}VIP_COLOR_DEPTH;
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struct rk_edp_platform_data {
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unsigned int dvdd33_en_pin;
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int dvdd33_en_val;
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unsigned int dvdd18_en_pin;
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int dvdd18_en_val;
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unsigned int edp_rst_pin;
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int (*power_ctl)(void);
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};
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struct rk_edp {
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struct i2c_client *client;
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struct rk_edp_platform_data *pdata;
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#ifdef CONFIG_HAS_EARLYSUSPEND
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struct early_suspend early_suspend;
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#endif
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};
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#endif
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