193 lines
5.1 KiB
C
Executable File
193 lines
5.1 KiB
C
Executable File
/*
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* Allwinner SoCs timer handling.
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*
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* Copyright (C) 2012 Maxime Ripard
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* Copyright (C) 2014 Superm Wu
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* Superm Wu <superm@allwinnertech.com>
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*
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* Based on code from
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* Benn Huang <benn@allwinnertech.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/clk.h>
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#include <linux/clockchips.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqreturn.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/clk/sunxi.h>
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#include <linux/delay.h>
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#define TIMER_IRQ_EN_REG 0x00
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#define TIMER_IRQ_EN(val) (1 << val)
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#define TIMER_IRQ_ST_REG 0x04
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#define TIMER_IRQ_ST(val) (1 << val)
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#define TIMER_CTL_REG(val) (0x10 * val + 0x10)
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#define TIMER_CTL_ENABLE (1 << 0)
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#define TIMER_CTL_AUTORELOAD (1 << 1)
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#define TIMER_CTL_MODE_MASK (1 << 7)
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#define TIMER_CTL_PERIODIC (0 << 7)
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#define TIMER_CTL_ONESHOT (1 << 7)
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#define TIMER_INTVAL_REG(val) (0x10 * val + 0x14)
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#define TIMER_CNTVAL_REG(val) (0x10 * val + 0x18)
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static int timer_nr = 0;
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static void __iomem *timer_base;
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#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
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extern void tick_broadcast(const struct cpumask *mask);
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#else
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#define tick_broadcast NULL
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#endif
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static void sunxi_clkevt_mode(enum clock_event_mode mode,
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struct clock_event_device *clk)
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{
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u32 u = readl(timer_base + TIMER_CTL_REG(timer_nr));
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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u &= ~(TIMER_CTL_MODE_MASK);
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writel(u | TIMER_CTL_ENABLE | TIMER_CTL_PERIODIC,
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timer_base + TIMER_CTL_REG(timer_nr));
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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u &= ~(TIMER_CTL_MODE_MASK);
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writel(u | TIMER_CTL_ONESHOT, timer_base + TIMER_CTL_REG(timer_nr));
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break;
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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default:
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writel(u & ~(TIMER_CTL_ENABLE), timer_base + TIMER_CTL_REG(timer_nr));
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break;
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}
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}
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static int sunxi_clkevt_next_event(unsigned long evt,
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struct clock_event_device *unused)
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{
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volatile u32 ctrl = 0;
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if(unused){
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/* set timer intervalue */
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writel(evt,(timer_base + TIMER_INTVAL_REG(timer_nr)));
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/*enable timer*/
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ctrl = readl(timer_base + TIMER_CTL_REG(timer_nr));
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ctrl |= TIMER_CTL_AUTORELOAD | TIMER_CTL_ENABLE;
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writel(ctrl,(timer_base + TIMER_CTL_REG(timer_nr)));
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}else{
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pr_warn("[%s][line-%d]set next event error!\n",__func__,__LINE__);
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BUG();
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return -EINVAL;
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}
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return 0;
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}
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static struct clock_event_device sunxi_clockevent = {
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.name = "sunxi_tick",
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.shift = 32,
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.rating = 300,
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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.set_mode = sunxi_clkevt_mode,
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.set_next_event = sunxi_clkevt_next_event,
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.broadcast = tick_broadcast,
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};
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static irqreturn_t sunxi_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = (struct clock_event_device *)dev_id;
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writel(TIMER_IRQ_ST(timer_nr), timer_base + TIMER_IRQ_ST_REG);
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static struct irqaction sunxi_timer_irq = {
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.name = "sunxi_timer",
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.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
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.handler = sunxi_timer_interrupt,
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.dev_id = &sunxi_clockevent,
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};
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static void __init sunxi_timer_init(struct device_node *node)
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{
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u32 rate = 0;
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u32 prescale = 0;
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int ret, irq;
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u32 val;
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timer_nr = of_alias_get_id(node, "global_timer");
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if (timer_nr < 0) {
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pr_err("Get soc_timer number error! timer_nr:%d\n", timer_nr);
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return;
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}
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if (of_property_read_u32(node, "clock-frequency", &rate)) {
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pr_err("<%s> must have a clock-frequency property\n", node->name);
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return;
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}
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if (of_property_read_u32(node, "timer-prescale", &prescale)) {
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pr_err("<%s> must have a timer-prescale property\n", node->name);
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return;
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}
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timer_base = of_iomap(node, 0);
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if (!timer_base)
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panic("Can't map registers");
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irq = irq_of_parse_and_map(node, 0);
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if (irq <= 0)
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panic("Can't parse IRQ");
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writel(rate / (prescale * HZ),
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timer_base + TIMER_INTVAL_REG(timer_nr));
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/* set clock source to HOSC, 16 pre-division */
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val = readl(timer_base + TIMER_CTL_REG(timer_nr));
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val &= ~(0x07 << 4);
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val &= ~(0x03 << 2);
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val |= (4 << 4) | (1 << 2);
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writel(val, timer_base + TIMER_CTL_REG(timer_nr));
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/* set mode to auto reload */
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val = readl(timer_base + TIMER_CTL_REG(timer_nr));
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writel(val | TIMER_CTL_AUTORELOAD, timer_base + TIMER_CTL_REG(timer_nr));
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ret = setup_irq(irq, &sunxi_timer_irq);
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if (ret)
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pr_warn("failed to setup irq %d\n", irq);
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/* Enable timer interrupt */
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val = readl(timer_base + TIMER_IRQ_EN_REG);
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writel(val | TIMER_IRQ_EN(timer_nr), timer_base + TIMER_IRQ_EN_REG);
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sunxi_clockevent.mult = div_sc(rate / prescale,
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NSEC_PER_SEC,
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sunxi_clockevent.shift);
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sunxi_clockevent.max_delta_ns = clockevent_delta2ns(0x7fffffff,
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&sunxi_clockevent);
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sunxi_clockevent.min_delta_ns = clockevent_delta2ns(0x10,
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&sunxi_clockevent);
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sunxi_clockevent.cpumask = cpumask_of(0);
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clockevents_register_device(&sunxi_clockevent);
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}
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CLOCKSOURCE_OF_DECLARE(sunxi, "allwinner,sunxi-timer",
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sunxi_timer_init);
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