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Changes for MMC BSP 3.0 driver

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This commit is contained in:
Dimitar Gamishev 2018-12-05 11:52:01 +02:00
parent 48e8d71526
commit e19b0611d7
3 changed files with 175 additions and 100 deletions
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51
SOFTWARE/A64-TERES/u-boot_new/include/mmc.h
View File

@ -33,6 +33,7 @@
#define MMC_VERSION_4_5 (MMC_VERSION_MMC | 0x405)
#define MMC_VERSION_5_0 (MMC_VERSION_MMC | 0x500)
#define MMC_VERSION_5_1 (MMC_VERSION_MMC | 0x501)
#define MMC_VERSION_NEW_VER (MMC_VERSION_MMC | 0xFFF)
#define MMC_MODE_HS (1 << 0) /* can run at 26MHz -- DS26_SDR12*/
#define MMC_MODE_HS_52MHz (1 << 1) /* can run at 52MHz with SDR mode -- HSSDR52_SDR25 */
@ -195,6 +196,9 @@
#define EXT_CSD_REV 192 /* RO */
#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
#define EXT_CSD_SECURE_REMOAL_TYPE 16 /* R/W */
#define EXT_CSD_FFU_STATUS 26 /* RO */
#define EXT_CSD_MODE_OPERATION_CODES 29 /* W */
#define EXT_CSD_MODE_CONFIG 30 /* R/W */
#define EXT_CSD_FLUSH_CACHE 32 /* W */
#define EXT_CSD_CACHE_CTRL 33 /* R/W */
#define EXT_CSD_POWER_OFF_NOTIFICATION 34 /* R/W */
@ -213,6 +217,7 @@
#define EXT_CSD_SANITIZE_START 165 /* W */
#define EXT_CSD_WR_REL_PARAM 166 /* RO */
#define EXT_CSD_RPMB_MULT 168 /* RO */
#define EXT_CSD_FW_CONFIG 169 /* R/W */
#define EXT_CSD_BOOT_WP 173 /* R/W */
#define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */
#define EXT_CSD_PART_CONFIG 179 /* R/W */
@ -249,10 +254,16 @@
#define EXT_CSD_GENERIC_CMD6_TIME 248 /* RO */
#define EXT_CSD_CACHE_SIZE 249 /* RO, 4 bytes */
#define EXT_CSD_PWR_CL_DDR_200_360 253 /* RO */
#define EXT_CSD_FIRMWARE_VERSION 254 /* 254-261, RO */
#define EXT_CSD_PRE_EOL_INFO 267 /* RO */
#define EXT_CSD_DEVICE_LIFE_TIME_EST_TYP_A 268 /* RO */
#define EXT_CSD_DEVICE_LIFE_TIME_EST_TYP_B 269 /* RO */
#define EXT_CSD_VENDOR_HEALTH_REPORT 270 /* 270-301, RO */
#define EXT_CSD_NUM_OF_FW_SECTS_PROGRAMMED /* 302-305, RO */
#define EXT_CSD_FFU_ARG 487 /* 487-490, RO */
#define EXT_CSD_OPERATION_CODES_TIMEOUT 491 /* RO */
#define EXT_CSD_FFU_FEATURES 492 /* RO */
#define EXT_CSD_SUPPORTED_MODES 493 /* RO */
#define EXT_CSD_TAG_UNIT_SIZE 498 /* RO */
#define EXT_CSD_DATA_TAG_SUPPORT 499 /* RO */
#define EXT_CSD_MAX_PACKED_WRITES 500 /* RO */
@ -324,6 +335,15 @@
#define EXT_CSD_SEC_GB_CL_EN (1U << 4)
#define EXT_CSD_SEC_SANITIZE (1U << 6) /* v4.5 only */
/* -- EXT_CSD[29] MODE_OPERATION_CODES */
#define EXT_CSD_FFU_INSTALL (1U << 1)
#define EXT_CSD_FFU_ABORT (1U << 2)
/* -- EXT_CSD[30] MODE_CONFIG */
#define EXT_CSD_NORMAL_MODE (0)
#define EXT_CSD_FFU_MODE (1)
#define EXT_CSD_VENDOR_SPECIFIC_MODE (2)
/* MMC_SWITCH boot modes */
#define MMC_SWITCH_MMCPART_NOAVAILABLE (0xff)
#define MMC_SWITCH_PART_ACCESS_MASK (0x7)
@ -475,7 +495,7 @@ struct tune_sdly {
u32 tm4_sm4_f3210;
u32 tm4_sm4_f7654;
*/
u32 tm4_smx_fx[10];
u32 tm4_smx_fx[12];
};
struct boot_mmc_cfg {
@ -498,6 +518,15 @@ struct boot_sdmmc_private_info_t {
#define CARD_TYPE_MMC 0x8000000
#define CARD_TYPE_NULL 0xffffffff
u32 card_type; /*0xffffffff: invalid; 0x8000000: mmc card; 0x8000001: sd card*/
#define EXT_PARA0_ID (0x55000000)
#define EXT_PARA0_TUNING_SUCCESS_FLAG (1U<<0)
u32 ext_para0;
/* ext_para1/2/3 reseved for future */
u32 ext_para1;
u32 ext_para2;
u32 ext_para3;
};
#endif
@ -544,7 +573,8 @@ struct mmc_platform_caps {
u8 tm4_tune_r_cycle;
u8 tm4_tune_hs200_max_freq;
u8 tm4_tune_hs400_max_freq;
u8 res[2];
u8 tune_limit_kernel_timing;
u8 res[1];
/* bit31: valid; bit23~16: speed mode; bit15~8: freq id; bit7:0 freq value */
#define MAX_EXT_FREQ_POINT_NUM (4)
@ -562,6 +592,17 @@ struct mmc_platform_caps {
u32 host_caps_mask;
struct tune_sdly sdly;
u32 force_boot_tuning;
/* enable the flow of field firmware update(FFU) flow */
u32 enable_ffu;
/* the byte length of emmc firmware, if it is 0, use the length get from toc0 header. if it is 0xffffffff, invalid len */
u32 emmc_fw_byte_len;
/* emmc_fw_ver0[31:0] = ext_csd[257] | ext_csd[256] | ext_csd[255] | ext_csd[254] */
u32 emmc_fw_ver0;
/* emmc_fw_ver1[31:0] = ext_csd[261] | ext_csd[260] | ext_csd[259] | ext_csd[258] */
u32 emmc_fw_ver1;
};
struct mmc_config {
@ -643,6 +684,7 @@ struct mmc {
u32 pll_clock;
u32 msglevel;
u32 do_tuning;
u32 tuning_end;
};
struct mmc_ext_csd {
@ -822,9 +864,14 @@ int mmc_send_manual_stop(struct mmc *mmc);
int sunxi_need_rty(struct mmc *mmc);
int sunxi_write_tuning(struct mmc *mmc);
int sunxi_bus_tuning(struct mmc *mmc);
unsigned int sunxi_select_freq(struct mmc *mmc, int speed_md, int freq_index);
int sunxi_switch_to_best_bus(struct mmc *mmc);
int sunxi_mmc_tuning_init(void);
int sunxi_mmc_tuning_exit(void);
int mmc_init_product(struct mmc *mmc);
int mmc_exit(void);
void mmc_update_config_for_sdly(struct mmc *mmc);
void mmc_update_config_for_dragonboard(int card_no);
#endif /* _MMC_H_ */

23
SOFTWARE/A64-TERES/u-boot_new/include/spare_head.h
View File

@ -34,6 +34,7 @@
#define WORK_MODE_CARD_PRODUCT 0x11 //用于卡量产
#define WORK_MODE_USB_DEBUG 0x12 //利用usb量产协议完成的测试
#define WORK_MODE_SPRITE_RECOVERY 0x13 //一键恢复
#define WORK_MODE_CARD_UPDATE 0x14 //update firmware from sdcard
#define WORK_MODE_USB_UPDATE 0x20 //用于USB升级
#define WORK_MODE_OUTER_UPDATE 0x21 //用于外部盘升级
@ -59,6 +60,12 @@
#define SUNXI_VBUS_NOT_EXIST (2)
#define BOOT0_SDMMC_START_ADDR (16)
#define BOOT0_SDMMC_BACKUP_START_ADDR (256)
#define BOOT0_EMMC3_START_ADDR (384)
#define BOOT0_EMMC3_BACKUP_START_ADDR (512)
#ifndef CONFIG_SUNXI_SECURE_SYSTEM
#define UBOOT_START_SECTOR_IN_SDMMC (38192)
#else
@ -66,10 +73,22 @@
#define UBOOT_START_SECTOR_PRE_IN_SDMMC (38192)
#endif
#define SUNXI_NORMAL_MODE 0
#define SUNXI_SECURE_MODE_WITH_SECUREOS 1
#define SUNXI_SECURE_MODE_NO_SECUREOS 2
typedef enum _SUNXI_BOOT_FILE_MODE
{
SUNXI_BOOT_FILE_NORMAL =0,
SUNXI_BOOT_FILE_TOC = 1,
SUNXI_BOOT_FILE_RES0 = 2,
SUNXI_BOOT_FILE_RES1 = 3,
SUNXI_BOOT_FILE_PKG = 4
}SUNXI_BOOT_FILE_MODE;
#define BOOT_FROM_SD0 0
#define BOOT_FROM_SD2 2
#define BOOT_FROM_NFC 1
@ -87,6 +106,7 @@
#define TOC_ITEM_ENTRY_TYPE_KEY_CERTIF 0x01
#define TOC_ITEM_ENTRY_TYPE_BIN_CERTIF 0x02
#define TOC_ITEM_ENTRY_TYPE_BIN 0x03
#define TOC_ITEM_ENTRY_TYPE_LOGO 0x04
typedef struct _normal_gpio_cfg
{
@ -122,7 +142,8 @@ typedef enum
STORAGE_NAND =0,
STORAGE_SD,
STORAGE_EMMC,
STORAGE_NOR
STORAGE_NOR,
STORAGE_EMMC3
}SUNXI_BOOT_STORAGE;
#endif

11
SOFTWARE/A64-TERES/u-boot_new/include/sys_config.h
View File

@ -38,14 +38,21 @@
#define FDT_PATH_CARD0_BOOT_PARA "/soc/card0_boot_para"
#define FDT_PATH_CARD2_BOOT_PARA "/soc/card2_boot_para"
#define FDT_PATH_REGU "/soc/regu"
/*
* mmc2 and mmc3 can be use only one at same time on sun8iw10, so put mmc3's config at the same
* place with mmc2 to be compatile with other platforms.
*/
#define FDT_PATH_CARD3_BOOT_PARA "/soc/card2_boot_para"
//for disp alias
#define FDT_DISP_PATH "disp"
#define FDT_HDMI_PATH "hdmi"
#define FDT_LCD0_PATH "lcd0"
#define FDT_LCD1_PATH "lcd1"
#define FDT_AC200_PATH "ac200"
#define FDT_BOOT_DISP_PATH "boot_disp"
#define FDT_TV0_PATH "tv0"
#define FDT_TV1_PATH "tv1"
@ -159,7 +166,7 @@ int fdt_get_one_gpio(const char* node_path, const char* prop_name,user_gpio_set_
int fdt_set_one_gpio(const char* node_path, const char* prop_name);
//pin for use fdt
//int fdt_get_pin_num(const char* node_path,const char* pinctrl_name);
//int fdt_get_all_pin(const char* node_path,const char* pinctrl_name,user_gpio_set_t* gpio_list);
int fdt_get_all_pin(int nodeoffset,const char* pinctrl_name,user_gpio_set_t* gpio_list);
int fdt_set_all_pin(const char * node_path,const char * pinctrl_name);
int fdt_set_all_pin_by_offset(int nodeoffset,const char* pinctrl_name);
int fdt_set_pin_byname(user_gpio_set_t *pin_list,int pin_count, const char* pin_name);