25 lines
1.0 KiB
Markdown
25 lines
1.0 KiB
Markdown
# What's next?
|
|
|
|
This product is a [work-in-progress](evaluation-board-notice.md).
|
|
|
|
## More capability
|
|
|
|
We are designing new main boards with newer and more powerful processors with more RAM and NAND flash (the trade-off would be a shorter battery life, of course).
|
|
|
|
TERES-I comes with 1376x768 LCD configuration.
|
|
Future main boards aim at 1920x1080 pixels.
|
|
|
|
## More extensibility
|
|
|
|
A set of expansion boards are being considered that can turn the TERES-I into a "portable lab".
|
|
This may include capabilities such as a digital storage oscilloscope and logic analyzer.
|
|
|
|
Different main board configurations: the first iteration comes with ARM64 and x86 support.
|
|
The MIPS architecture is coming soon with other architectures to follow.
|
|
The concept is to make templates which others may use to customize so other SOCs may be used for a main board.
|
|
|
|
## More adoption
|
|
|
|
Being OSHW, community members are welcome to release their own ideas, software and hardware projects and designs compatible with the TERES-I.
|
|
We would love for you to help [contribute](../../CONTRIBUTING.md)!
|