506 lines
12 KiB
C
Executable File
506 lines
12 KiB
C
Executable File
/* Copyright (C) 2014 ALLWINNERTECH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/gpio.h>
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#include <linux/slab.h>
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#include <linux/clk.h>
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#include <linux/of_gpio.h>
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#include <linux/platform_device.h>
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#include <linux/regulator/consumer.h>
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#include <linux/irq.h>
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#include <linux/of_platform.h>
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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#include <media/rc-core.h>
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#include "sunxi-ir-rx.h"
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#define SUNXI_IR_DRIVER_NAME "sunxi-rc-recv"
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#define SUNXI_IR_DEVICE_NAME "sunxi_ir_recv"
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DEFINE_IR_RAW_EVENT(rawir);
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static struct sunxi_ir_data *ir_data;
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static struct rc_dev *sunxi_rcdev;
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static u32 is_receiving = 0;
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static bool pluse_pre = 0;
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static char ir_dev_name[] = "s_cir_rx";
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static int debug_mask = 0;
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#define dprintk(level_mask, fmt, arg...) if (unlikely(debug_mask & level_mask)) \
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printk(fmt , ## arg)
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#define IR_BASE (ir_data->reg_base)
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static inline u8 ir_get_data(void)
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{
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return (u8)(readl(IR_BASE + IR_RXDAT_REG));
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}
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static inline u32 ir_get_intsta(void)
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{
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return (readl(IR_BASE + IR_RXINTS_REG));
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}
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static inline void ir_clr_intsta(u32 bitmap)
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{
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u32 tmp = readl(IR_BASE + IR_RXINTS_REG);
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tmp &= ~0xff;
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tmp |= bitmap&0xff;
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writel(tmp, IR_BASE + IR_RXINTS_REG);
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}
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#ifdef CONFIG_OF
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/* Translate OpenFirmware node properties into platform_data */
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static struct of_device_id sunxi_ir_recv_of_match[] = {
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{ .compatible = "allwinner,s_cir", },
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{ },
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};
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MODULE_DEVICE_TABLE(of, sunxi_ir_recv_of_match);
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#else /* !CONFIG_OF */
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#endif
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static irqreturn_t sunxi_ir_recv_irq(int irq, void *dev_id)
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{
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u32 intsta,dcnt;
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u32 i = 0;
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bool pluse_now = 0;
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u8 reg_data;
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dprintk(DEBUG_INT, "IR RX IRQ Serve\n");
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intsta = ir_get_intsta();
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ir_clr_intsta(intsta);
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/* get ther count of signal */
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dcnt = (intsta>>8) & 0x7f;
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dprintk(DEBUG_INT, "receive cnt :%d \n", dcnt);
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/* Read FIFO and fill the raw event */
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for (i=0; i<dcnt; i++) {
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/* get the data from fifo */
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reg_data = ir_get_data();
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pluse_now = (reg_data & 0x80)? true : false;
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if( pluse_pre == pluse_now){/* the signal maintian */
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/* the pluse or space lasting*/
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rawir.duration += (u32)(reg_data & 0x7f);
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dprintk(DEBUG_ERR,"raw: %d:%d \n",(reg_data & 0x80)>>7,(reg_data & 0x7f));
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}else{
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if(is_receiving){
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rawir.duration *= IR_SIMPLE_UNIT;
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dprintk(DEBUG_INT,"pusle :%d, dur: %u ns\n",rawir.pulse,rawir.duration );
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ir_raw_event_store(sunxi_rcdev, &rawir);
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rawir.pulse = pluse_now;
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rawir.duration = (u32)(reg_data & 0x7f);
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dprintk(DEBUG_ERR,"raw: %d:%d \n",(reg_data & 0x80)>>7,(reg_data & 0x7f));
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}else{
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/* get the first pluse signal */
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rawir.pulse = pluse_now;
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rawir.duration = (u32)(reg_data & 0x7f);
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#ifdef CIR_FPGA
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rawir.duration += ((IR_ACTIVE_T>>16)+1) * ((IR_ACTIVE_T_C>>23 )? 128:1);
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dprintk(DEBUG_INT, "get frist pulse,add head %d !!\n",((IR_ACTIVE_T>>16)+1) * ((IR_ACTIVE_T_C>>23 )? 128:1));
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#endif
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is_receiving = 1;
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dprintk(DEBUG_ERR,"raw: %d:%d \n",(reg_data & 0x80)>>7,(reg_data & 0x7f));
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}
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pluse_pre = pluse_now;
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}
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}
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if (intsta & IR_RXINTS_RXPE){
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if(rawir.duration){
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rawir.duration *= IR_SIMPLE_UNIT;
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dprintk(DEBUG_INT,"pusle :%d, dur: %u ns\n",rawir.pulse,rawir.duration );
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ir_raw_event_store(sunxi_rcdev, &rawir);
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}
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dprintk(DEBUG_INT, "handle raw data.\n");
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/* handle ther decoder theread */
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ir_raw_event_handle(sunxi_rcdev);
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is_receiving = 0;
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pluse_pre = false;
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}
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if (intsta & IR_RXINTS_RXOF) {
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/* FIFO Overflow */
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pr_err("ir_rx_irq_service: Rx FIFO Overflow!!\n");
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is_receiving = 0;
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pluse_pre = false;
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}
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return IRQ_HANDLED;
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}
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static void ir_mode_set(enum ir_mode set_mode)
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{
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u32 ctrl_reg = 0;
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switch (set_mode) {
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case CIR_MODE_ENABLE:
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ctrl_reg = readl(IR_BASE+IR_CTRL_REG);
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ctrl_reg |= IR_CIR_MODE;
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break;
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case IR_MODULE_ENABLE:
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ctrl_reg = readl(IR_BASE+IR_CTRL_REG);
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ctrl_reg |= IR_ENTIRE_ENABLE;
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break;
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default:
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return;
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}
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writel(ctrl_reg, IR_BASE+IR_CTRL_REG);
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}
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static void ir_sample_config(enum ir_sample_config set_sample)
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{
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u32 sample_reg = 0;
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sample_reg = readl(IR_BASE+IR_SPLCFG_REG);
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switch (set_sample) {
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case IR_SAMPLE_REG_CLEAR:
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sample_reg = 0;
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break;
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case IR_CLK_SAMPLE:
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sample_reg |= IR_SAMPLE_DEV;
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break;
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case IR_FILTER_TH:
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sample_reg |= IR_RXFILT_VAL;
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break;
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case IR_IDLE_TH:
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sample_reg |= IR_RXIDLE_VAL;
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break;
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case IR_ACTIVE_TH:
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sample_reg |= IR_ACTIVE_T;
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sample_reg |= IR_ACTIVE_T_C;
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break;
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default:
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return;
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}
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writel(sample_reg, IR_BASE+IR_SPLCFG_REG);
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}
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static void ir_signal_invert(void)
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{
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u32 reg_value;
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reg_value = 0x1<<2;
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writel(reg_value, IR_BASE+IR_RXCFG_REG);
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}
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static void ir_irq_config(enum ir_irq_config set_irq)
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{
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u32 irq_reg = 0;
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switch (set_irq) {
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case IR_IRQ_STATUS_CLEAR:
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writel(0xef, IR_BASE+IR_RXINTS_REG);
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return;
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case IR_IRQ_ENABLE:
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irq_reg = readl(IR_BASE+IR_RXINTE_REG);
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irq_reg |= IR_IRQ_STATUS;
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break;
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case IR_IRQ_FIFO_SIZE:
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irq_reg = readl(IR_BASE+IR_RXINTE_REG);
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irq_reg |= IR_FIFO_32;
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break;
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default:
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return;
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}
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writel(irq_reg, IR_BASE+IR_RXINTE_REG);
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}
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static void ir_reg_cfg(void)
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{
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/* Enable IR Mode */
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ir_mode_set(CIR_MODE_ENABLE);
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/* Config IR Smaple Register */
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ir_sample_config(IR_SAMPLE_REG_CLEAR);
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ir_sample_config(IR_CLK_SAMPLE);
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ir_sample_config(IR_FILTER_TH); /* Set Filter Threshold */
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ir_sample_config(IR_IDLE_TH); /* Set Idle Threshold */
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ir_sample_config(IR_ACTIVE_TH); /* Set Active Threshold */
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/* Invert Input Signal */
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ir_signal_invert();
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/* Clear All Rx Interrupt Status */
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ir_irq_config(IR_IRQ_STATUS_CLEAR);
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/* Set Rx Interrupt Enable */
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ir_irq_config(IR_IRQ_ENABLE);
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ir_irq_config(IR_IRQ_FIFO_SIZE); /* Rx FIFO Threshold = FIFOsz/2; */
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/* Enable IR Module */
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ir_mode_set(IR_MODULE_ENABLE);
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return;
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}
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static void ir_clk_cfg(void)
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{
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unsigned long rate = 0;
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rate = clk_get_rate(ir_data->pclk);
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dprintk(DEBUG_INIT, "%s: get ir_clk_source rate %dHZ\n", __func__, (__u32)rate);
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if(clk_set_parent(ir_data->mclk, ir_data->pclk))
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pr_err("%s: set ir_clk parent to ir_clk_source failed!\n", __func__);
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if (clk_set_rate(ir_data->mclk, IR_CLK)) {
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pr_err("set ir clock freq to 4M failed!\n");
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}
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rate = clk_get_rate(ir_data->mclk);
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dprintk(DEBUG_INIT, "%s: get ir_clk rate %dHZ\n", __func__, (__u32)rate);
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if (clk_prepare_enable(ir_data->mclk)) {
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pr_err("try to enable ir_clk failed!\n");
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}
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return;
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}
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static void ir_clk_uncfg(void)
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{
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if(NULL == ir_data->mclk || IS_ERR(ir_data->mclk)) {
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pr_err("ir_clk handle is invalid, just return!\n");
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return;
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} else {
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clk_disable_unprepare(ir_data->mclk);
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clk_put(ir_data->mclk);
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ir_data->mclk = NULL;
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}
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if(NULL == ir_data->pclk || IS_ERR(ir_data->pclk)) {
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pr_err("ir_clk_source handle is invalid, just return!\n");
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return;
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} else {
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clk_put(ir_data->pclk);
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ir_data->pclk = NULL;
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}
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return;
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}
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static void ir_setup(void)
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{
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dprintk(DEBUG_INIT, "ir_rx_setup: ir setup start!!\n");
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ir_clk_cfg();
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ir_reg_cfg();
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dprintk(DEBUG_INIT, "ir_rx_setup: ir setup end!!\n");
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return;
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}
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static int sunxi_ir_startup(struct platform_device *pdev)
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{
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struct device_node *np =NULL;
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int ret = 0;
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const char *name = NULL;
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ir_data = kzalloc(sizeof(*ir_data), GFP_KERNEL);
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if (IS_ERR_OR_NULL(ir_data)) {
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pr_err("ir_data: not enough memory for ir data\n");
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return -ENOMEM;
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}
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np = pdev->dev.of_node;
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ir_data->reg_base= of_iomap(np, 0);
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if (NULL == ir_data->reg_base) {
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pr_err("%s:Failed to ioremap() io memory region.\n",__func__);
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ret = -EBUSY;
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}else
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dprintk(DEBUG_INIT, "ir base: %p !\n",ir_data->reg_base);
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ir_data->irq_num= irq_of_parse_and_map(np, 0);
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if (0 == ir_data->irq_num) {
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pr_err("%s:Failed to map irq.\n", __func__);
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ret = -EBUSY;
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}else
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dprintk(DEBUG_INIT, "ir irq num: %d !\n",ir_data->irq_num);
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ir_data->pclk = of_clk_get(np, 0);
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ir_data->mclk = of_clk_get(np, 1);
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if (NULL==ir_data->pclk||IS_ERR(ir_data->pclk)
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||NULL==ir_data->mclk||IS_ERR(ir_data->mclk)) {
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pr_err("%s:Failed to get clk.\n", __func__);
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ret = -EBUSY;
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}
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if (of_property_read_u32(np, "ir_addr_code", &ir_data->ir_addr)) {
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pr_err("%s: get cir addr failed", __func__);
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ret = -EBUSY;
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}
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if (of_property_read_string(np, "supply", &name)) {
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pr_err("%s: cir have no power supply\n", __func__);
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ir_data->suply = NULL;
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}else{
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ir_data->suply = regulator_get(NULL, name);
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if(IS_ERR(ir_data->pclk)){
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pr_err("%s: cir get supply err\n", __func__);
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ir_data->suply = NULL;
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}
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}
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return ret;
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}
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static int sunxi_ir_recv_probe(struct platform_device *pdev)
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{
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int rc;
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dprintk(DEBUG_INIT, "sunxi-ir probe start !\n");
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if (pdev->dev.of_node) {
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/* get dt and sysconfig */
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rc = sunxi_ir_startup(pdev);
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}else{
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pr_err("sunxi ir device tree err!\n");
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return -EBUSY;
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}
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if( rc < 0)
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goto err_allocate_device;
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sunxi_rcdev = rc_allocate_device();
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if (!sunxi_rcdev) {
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rc = -ENOMEM;
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pr_err("rc dev allocate fail !\n");
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goto err_allocate_device;
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}
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sunxi_rcdev->driver_type = RC_DRIVER_IR_RAW;
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sunxi_rcdev->input_name = SUNXI_IR_DEVICE_NAME;
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sunxi_rcdev->input_phys = SUNXI_IR_DEVICE_NAME "/input0";
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sunxi_rcdev->input_id.bustype = BUS_HOST;
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sunxi_rcdev->input_id.vendor = 0x0001;
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sunxi_rcdev->input_id.product = 0x0001;
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sunxi_rcdev->input_id.version = 0x0100;
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sunxi_rcdev->dev.parent = &pdev->dev;
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sunxi_rcdev->driver_name = SUNXI_IR_DRIVER_NAME;
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sunxi_rcdev->allowed_protos = (u64)RC_BIT_NEC;
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sunxi_rcdev->map_name = RC_MAP_SUNXI;
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init_rc_map_sunxi(ir_data->ir_addr);
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rc = rc_register_device(sunxi_rcdev);
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if (rc < 0) {
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dev_err(&pdev->dev, "failed to register rc device\n");
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goto err_register_rc_device;
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}
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sunxi_rcdev->enabled_protocols = sunxi_rcdev->allowed_protos;;
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sunxi_rcdev->input_dev->dev.init_name = &ir_dev_name[0];
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if (0 != rc) {
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pr_err("%s: config ir rx pin err.\n", __func__);
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goto err_platfrom_device;
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}
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platform_set_drvdata(pdev, sunxi_rcdev);
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ir_data->rcdev = sunxi_rcdev;
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if(ir_data->suply)
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rc = regulator_enable(ir_data->suply);
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ir_setup();
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if (request_irq(ir_data->irq_num, sunxi_ir_recv_irq, IRQF_DISABLED, "RemoteIR_RX",
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sunxi_rcdev)) {
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pr_err("%s: request irq fail.\n", __func__);
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rc = -EBUSY;
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goto err_request_irq;
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}
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/* enable here */
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dprintk(DEBUG_INIT, "ir probe end!\n");
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return 0;
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err_request_irq:
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platform_set_drvdata(pdev, NULL);
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rc_unregister_device(sunxi_rcdev);
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sunxi_rcdev = NULL;
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ir_clk_uncfg();
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if(ir_data->suply){
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regulator_disable(ir_data->suply);
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regulator_put(ir_data->suply);
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}
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err_platfrom_device:
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exit_rc_map_sunxi();
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err_register_rc_device:
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rc_free_device(sunxi_rcdev);
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err_allocate_device:
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if(ir_data)
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kfree(ir_data);
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return rc;
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}
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static int sunxi_ir_recv_remove(struct platform_device *pdev)
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{
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free_irq(ir_data->irq_num, sunxi_rcdev);
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ir_clk_uncfg();
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platform_set_drvdata(pdev, NULL);
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if(ir_data->suply){
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regulator_disable(ir_data->suply);
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regulator_put(ir_data->suply);
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}
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rc_unregister_device(sunxi_rcdev);
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exit_rc_map_sunxi();
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if(ir_data)
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kfree(ir_data);
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return 0;
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}
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#ifdef CONFIG_PM
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static int sunxi_ir_recv_suspend(struct device *dev)
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{
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dprintk(DEBUG_SUSPEND, "enter: sunxi_ir_rx_suspend. \n");
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disable_irq_nosync(ir_data->irq_num);
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if(NULL == ir_data->mclk || IS_ERR(ir_data->mclk)) {
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pr_err("ir_clk handle is invalid, just return!\n");
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return -1;
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} else {
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clk_disable_unprepare(ir_data->mclk);
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}
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return 0;
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}
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static int sunxi_ir_recv_resume(struct device *dev)
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{
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dprintk(DEBUG_SUSPEND, "enter: sunxi_ir_rx_resume. \n");
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clk_prepare_enable(ir_data->mclk);
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ir_reg_cfg();
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enable_irq(ir_data->irq_num);
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return 0;
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}
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static const struct dev_pm_ops sunxi_ir_recv_pm_ops = {
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.suspend = sunxi_ir_recv_suspend,
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.resume = sunxi_ir_recv_resume,
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};
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#endif
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static struct platform_driver sunxi_ir_recv_driver = {
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.probe = sunxi_ir_recv_probe,
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.remove = sunxi_ir_recv_remove,
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.driver = {
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.name = SUNXI_IR_DRIVER_NAME,
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.owner = THIS_MODULE,
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.of_match_table = of_match_ptr(sunxi_ir_recv_of_match),
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#ifdef CONFIG_PM
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.pm = &sunxi_ir_recv_pm_ops,
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#endif
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},
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};
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module_platform_driver(sunxi_ir_recv_driver);
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module_param_named(debug_mask, debug_mask, int, 0644);
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MODULE_DESCRIPTION("SUNXI IR Receiver driver");
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MODULE_AUTHOR("QIn");
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MODULE_LICENSE("GPL v2");
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