111 lines
2.8 KiB
C
111 lines
2.8 KiB
C
/*
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* arch/arm/mach-sunxi/platsmp.h
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*
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* Copyright(c) 2013-2015 Allwinnertech Co., Ltd.
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* http://www.allwinnertech.com
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*
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* Author: liugang <liugang@allwinnertech.com>
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*
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* sunxi smp ops header file
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef __PLAT_SMP_H
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#define __PLAT_SMP_H
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#define get_nr_cores() \
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({ \
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unsigned int __val; \
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asm("mrc p15, 1, %0, c9, c0, 2" \
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: "=r" (__val) \
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: \
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: "cc"); \
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((__val>>24) & 0x03) + 1; \
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})
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#define SUNXI_CPUCFG_PBASE (0x01C25C00)
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#define CPUCFG_CPUX_RST_CTRL(x) (0x40 + (x)*0x40)
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#define CPUCFG_CPUX_STATUS_REG(x) (0x48 + (x)*0x40)
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#define CPUCFG_GENER_CTRL_REG (0x184)
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#define CPUCFG_DEBUG_REG1 (0x1e4)
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#define SUNXI_RTC_PBASE (0x01C20400)
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#define CPU_SOFT_ENTRY_REG0 (0x1e4)
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extern void sunxi_cpu_die(unsigned int cpu);
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extern int sunxi_cpu_kill(unsigned int cpu);
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extern int sunxi_cpu_disable(unsigned int cpu);
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extern void __iomem *sunxi_cpucfg_base;
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extern void __iomem *sunxi_rtc_base;
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static inline void sunxi_set_secondary_entry(void *entry)
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{
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writel((u32)entry, sunxi_rtc_base + CPU_SOFT_ENTRY_REG0);
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}
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static inline int sunxi_is_wfi_mode(int cpu)
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{
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#ifdef CONFIG_EVB_PLATFORM
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return readl(sunxi_rtc_base + CPUCFG_CPUX_STATUS_REG(cpu)) & (1<<2);
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#else
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return 1;
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#endif
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}
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static inline void sunxi_enable_cpu(int cpu)
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{
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unsigned int value;
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/* Assert nCOREPORESET LOW and hold L1RSTDISABLE LOW.
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Ensure DBGPWRDUP is held LOW to prevent any external
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debug access to the processor.
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*/
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/* assert cpu core reset */
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writel(0, sunxi_cpucfg_base + CPUCFG_CPUX_RST_CTRL(cpu));
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/* L1RSTDISABLE hold low */
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value = readl(sunxi_cpucfg_base + CPUCFG_GENER_CTRL_REG);
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value &= ~(1<<cpu);
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writel(value, sunxi_cpucfg_base + CPUCFG_GENER_CTRL_REG);
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udelay(10);
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/* DBGPWRDUP hold low */
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value = readl(sunxi_cpucfg_base + CPUCFG_DEBUG_REG1);
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value &= ~(1<<cpu);
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writel(value, sunxi_cpucfg_base + CPUCFG_DEBUG_REG1);
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/* de-assert core reset */
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writel(3, sunxi_cpucfg_base + CPUCFG_CPUX_RST_CTRL(cpu));
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/* assert DBGPWRDUP signal */
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value = readl(sunxi_cpucfg_base + CPUCFG_DEBUG_REG1);
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value |= (1<<cpu);
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writel(value, sunxi_cpucfg_base + CPUCFG_DEBUG_REG1);
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}
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static inline void sunxi_disable_cpu(int cpu)
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{
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unsigned int value;
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/* assert cpu core reset */
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writel(0, sunxi_cpucfg_base + CPUCFG_CPUX_RST_CTRL(cpu));
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/* DBGPWRDUP hold low */
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value = readl(sunxi_cpucfg_base + CPUCFG_DEBUG_REG1);
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value &= ~(1<<cpu);
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writel(value, sunxi_cpucfg_base + CPUCFG_DEBUG_REG1);
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/* power gating off */
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/* power switch off */
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}
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#endif /* __PLAT_SMP_H */
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