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TERES/SOFTWARE/A64-TERES/linux-a64/arch/arm/boot/dts/sun8iw11p1.dtsi
Dimitar Gamishev f9b0e7a283 linux
2017-10-13 14:07:04 +03:00

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/*
* Allwinner Technology CO., Ltd. sun8iw11p1 platform
*
* fpga support
* modify base on juno.dts & sun8iw10
*/
/* kernel used */
/memreserve/ 0x45000000 0x00200000; /* sun8iw11p1.dtb range : [0x45000000~0x45200000], size = 2M */
/memreserve/ 0x41010000 0x00010000; /* sys_config.fex range : [0x41010000~0x41020000], size = 64K */
/memreserve/ 0x41020000 0x00000800; /* super standby range : [0x41020000~0x41020800], size = 2K */
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
#include "sun8iw11p1-clk.dtsi"
#include "sun8iw11p1-pinctrl.dtsi"
/ {
model = "sun8iw11p1";
compatible = "arm,sun8iw11p1", "arm,sun8iw11p1";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
aliases {
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
serial3 = &uart3;
serial4 = &uart4;
serial5 = &uart5;
serial6 = &uart6;
serial7 = &uart7;
twi0 = &twi0;
twi1 = &twi1;
twi2 = &twi2;
twi3 = &twi3;
twi4 = &twi4;
spi0 = &spi0;
spi1 = &spi1;
spi2 = &spi2;
spi3 = &spi3;
global_timer0 = &soc_timer0;
cci0 = &csi_cci0;
csi_res0 = &csi_res0;
csi_res1 = &csi_res1;
vfe0 = &csi0;
vfe1 = &csi1;
mmc0 = &sdc0;
mmc2 = &sdc2;
nand0 =&nand0;
disp = &disp;
lcd0 = &lcd0;
pwm = &pwm;
boot_disp = &boot_disp;
};
chosen {
bootargs = "earlyprintk=sunxi-uart,0x01c28000 loglevel=8 initcall_debug=1 console=ttyS0 init=/init";
linux,initrd-start = <0x0 0x0>;
linux,initrd-end = <0x0 0x0>;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x0>;
clock-latency = <2000000>;
clock-frequency = <1008000000>;
};
};
n_brom {
compatible = "allwinner,n-brom";
reg = <0x0 0x0 0x0 0xc000>;
};
s_brom {
compatible = "allwinner,s-brom";
reg = <0x0 0x0 0x0 0x10000>;
};
sram_a1 {
compatible = "allwinner,sram_a1";
reg = <0x0 0x00010000 0x0 0x8000>;
};
sram_a2 {
compatible = "allwinner,sram_a2";
reg = <0x0 0x00040000 0x0 0x14000>;
};
prcm {
compatible = "allwinner,prcm";
reg = <0x0 0x01f01400 0x0 0x400>;
};
cpuscfg {
compatible = "allwinner,cpuscfg";
reg = <0x0 0x01f01c00 0x0 0x400>;
};
ion {
compatible = "allwinner,sunxi-ion";
/*types is list here:
ION_HEAP_TYPE_SYSTEM = 0,
ION_HEAP_TYPE_SYSTEM_CONTIG = 1,
ION_HEAP_TYPE_CARVEOUT = 2,
ION_HEAP_TYPE_CHUNK = 3,
ION_HEAP_TYPE_DMA = 4
**/
system_contig{
type = <1>;
name = "system_contig";
};
cma{
type = <4>;
name = "cma";
};
system{
type = <0>;
name = "system";
};
};
dram: dram {
compatible = "allwinner,dram";
clocks = <&clk_pll_ddr0>, <&clk_pll_ddr1>;
clock-names = "pll_ddr0", "pll_ddr1";
dram_clk = <672>;
dram_type = <3>;
dram_zq = <0x003F3FDD>;
dram_odt_en = <1>;
dram_para1 = <0x10f41000>;
dram_para2 = <0x00001200>;
dram_mr0 = <0x1A50>;
dram_mr1 = <0x40>;
dram_mr2 = <0x10>;
dram_mr3 = <0>;
dram_tpr0 = <0x04E214EA>;
dram_tpr1 = <0x004214AD>;
dram_tpr2 = <0x10A75030>;
dram_tpr3 = <0>;
dram_tpr4 = <0>;
dram_tpr5 = <0>;
dram_tpr6 = <0>;
dram_tpr7 = <0>;
dram_tpr8 = <0>;
dram_tpr9 = <0>;
dram_tpr10 = <0>;
dram_tpr11 = <0>;
dram_tpr12 = <168>;
dram_tpr13 = <0x823>;
};
memory@40000000 {
device_type = "memory";
reg = <0x00000000 0x40000000 0x00000000 0x40000000>;
};
gic: interrupt-controller@1c81000 {
compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <0>;
device_type = "gic";
interrupt-controller;
reg = <0x0 0x01c81000 0 0x1000>, /* GIC Dist */
<0x0 0x01c82000 0 0x2000>, /* GIC CPU */
<0x0 0x01c84000 0 0x2000>, /* GIC VCPU Control */
<0x0 0x01c86000 0 0x2000>; /* GIC VCPU */
interrupts = <GIC_PPI 9 0xf04>; /* GIC Maintenence IRQ */
};
chipid: sunxi-chipid@1c14200 {
compatible = "sunxi,sun50i-chipid";
device_type = "chipid";
reg = <0x0 0x01c14200 0 0x0400>; /* chipid */
};
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 0xff01>, /* Secure Phys IRQ */
<GIC_PPI 14 0xff01>, /* Non-secure Phys IRQ */
<GIC_PPI 11 0xff01>, /* Virt IRQ */
<GIC_PPI 10 0xff01>; /* Hyp IRQ */
clock-frequency = <24000000>;
};
wdt: watchdog@01c20ca0 {
compatible = "allwinner,sun8i-wdt";
reg = <0x0 0x01c20ca0 0 0x18>;
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_SPI 120 4>,
<GIC_SPI 121 4>,
<GIC_SPI 122 4>,
<GIC_SPI 123 4>;
};
dvfs_table: dvfs_table {
compatible = "allwinner,dvfs_table";
max_freq = <1200000000>;
min_freq = <480000000>;
lv_count = <8>;
lv1_freq = <1200000000>;
lv1_volt = <1300>;
lv2_freq = <1008000000>;
lv2_volt = <1200>;
lv3_freq = <816000000>;
lv3_volt = <1100>;
lv4_freq = <648000000>;
lv4_volt = <1040>;
lv5_freq = <0>;
lv5_volt = <1040>;
lv6_freq = <0>;
lv6_volt = <1040>;
lv7_freq = <0>;
lv7_volt = <1040>;
lv8_freq = <0>;
lv8_volt = <1040>;
};
dramfreq {
compatible = "allwinner,sunxi-dramfreq";
reg = <0x0 0x01c62000 0x0 0x1000>,
<0x0 0x01c63000 0x0 0x1000>,
<0x0 0x01c20000 0x0 0x800>;
interrupts = <GIC_SPI 69 0x4>;
clocks = <&clk_pll_ddr0>,<&clk_pll_ddr1>,<&clk_ahb1>;
status = "okay";
};
uboot: uboot {
};
soc: soc@01c00000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
device_type = "soc";
dma0:dma-controller@01c02000 {
compatible = "allwinner,sun50i-dma";
reg = <0x0 0x01c02000 0x0 0x1000>;
interrupts = <GIC_SPI 27 4>;
clocks = <&clk_dma>;
#dma-cells = <1>;
};
mbus0:mbus-controller@01c62000 {
compatible = "allwinner,sun8i-mbus";
reg = <0x0 0x01c62000 0x0 0x110>;
#mbus-cells = <1>;
};
standby_space {
compatible = "allwinner,standby_space";
/* num dst offset size */
space1 = <0x41020000 0x00000000 0x00000800>; /* super standby para space */
};
soc_timer0: timer@1c20c00 {
compatible = "allwinner,sunxi-timer";
device_type = "timer";
reg = <0x0 0x01c20c00 0x0 0x90>;
interrupts = <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
clock-frequency = <24000000>;
timer-prescale = <16>;
};
rtc: rtc@01c20400 {
compatible = "allwinner,sun8i-rtc";
device_type = "rtc";
reg = <0x0 0x1c20400 0x0 0x218>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
gpr_offset = <0x100>;
gpr_len = <4>;
};
uart0: uart@01c28000 {
compatible = "allwinner,sun8i-uart";
device_type = "uart0";
reg = <0x0 0x01c28000 0x0 0x400>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_uart0>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&uart0_pins_a>;
pinctrl-1 = <&uart0_pins_b>;
uart0_port = <0>;
uart0_type = <2>;
status = "disabled";
};
uart1: uart@01c28400 {
compatible = "allwinner,sun8i-uart";
device_type = "uart1";
reg = <0x0 0x01c28400 0x0 0x400>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_uart1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&uart1_pins_a>;
pinctrl-1 = <&uart1_pins_b>;
uart1_port = <1>;
uart1_type = <8>;
status = "disabled";
};
uart2: uart@01c28800 {
compatible = "allwinner,sun8i-uart";
device_type = "uart2";
reg = <0x0 0x01c28800 0x0 0x400>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_uart2>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&uart2_pins_a>;
pinctrl-1 = <&uart2_pins_b>;
uart2_port = <2>;
uart2_type = <4>;
status = "disabled";
};
uart3: uart@01c28c00 {
compatible = "allwinner,sun8i-uart";
device_type = "uart3";
reg = <0x0 0x01c28c00 0x0 0x400>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_uart3>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&uart3_pins_a>;
pinctrl-1 = <&uart3_pins_b>;
uart3_port = <3>;
uart3_type = <4>;
status = "disabled";
};
uart4: uart@01c29000 {
compatible = "allwinner,sun8i-uart";
device_type = "uart4";
reg = <0x0 0x01c29000 0x0 0x400>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_uart4>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&uart4_pins_a>;
pinctrl-1 = <&uart4_pins_b>;
uart4_port = <4>;
uart4_type = <2>;
status = "disabled";
};
uart5: uart@01c29400 {
compatible = "allwinner,sun8i-uart";
device_type = "uart5";
reg = <0x0 0x01c29400 0x0 0x400>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_uart5>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&uart5_pins_a>;
pinctrl-1 = <&uart5_pins_b>;
uart5_port = <5>;
uart5_type = <2>;
status = "disabled";
};
uart6: uart@01c29800 {
compatible = "allwinner,sun8i-uart";
device_type = "uart6";
reg = <0x0 0x01c29800 0x0 0x400>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_uart6>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&uart6_pins_a>;
pinctrl-1 = <&uart6_pins_b>;
uart6_port = <6>;
uart6_type = <2>;
status = "disabled";
};
uart7: uart@01c29c00 {
compatible = "allwinner,sun8i-uart";
device_type = "uart7";
reg = <0x0 0x01c29c00 0x0 0x400>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_uart7>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&uart7_pins_a>;
pinctrl-1 = <&uart7_pins_b>;
uart7_port = <7>;
uart7_type = <2>;
status = "disabled";
};
twi0: twi@0x01c2ac00{
#address-cells = <1>;
#size-cells = <0>;
compatible = "allwinner,sun8i-twi";
device_type = "twi0";
reg = <0x0 0x01c2ac00 0x0 0x400>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_twi0>;
clock-frequency = <400000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&twi0_pins_a>;
pinctrl-1 = <&twi0_pins_b>;
status = "disabled";
};
twi1: twi@0x01c2b000{
#address-cells = <1>;
#size-cells = <0>;
compatible = "allwinner,sun8i-twi";
device_type = "twi1";
reg = <0x0 0x01c2b000 0x0 0x400>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_twi1>;
clock-frequency = <200000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&twi1_pins_a>;
pinctrl-1 = <&twi1_pins_b>;
status = "disabled";
};
twi2: twi@0x01c2b400{
#address-cells = <1>;
#size-cells = <0>;
compatible = "allwinner,sun50i-twi";
device_type = "twi2";
reg = <0x0 0x01c2b400 0x0 0x400>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_twi2>;
clock-frequency = <200000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&twi2_pins_a>;
pinctrl-1 = <&twi2_pins_b>;
status = "disabled";
};
twi3: twi@0x01c2b800{
#address-cells = <1>;
#size-cells = <0>;
compatible = "allwinner,sun8i-twi";
device_type = "twi3";
reg = <0x0 0x01c2b800 0x0 0x400>;
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_twi3>;
clock-frequency = <200000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&twi3_pins_a>;
pinctrl-1 = <&twi3_pins_b>;
status = "disabled";
};
twi4: twi@0x01c2c000{
#address-cells = <1>;
#size-cells = <0>;
compatible = "allwinner,sun8i-twi";
device_type = "twi4";
reg = <0x0 0x01c2c000 0x0 0x400>;
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_twi4>;
clock-frequency = <200000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&twi4_pins_a>;
pinctrl-1 = <&twi4_pins_b>;
status = "disabled";
};
spi0: spi@01c05000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "allwinner,sun8i-spi";
device_type = "spi0";
reg = <0x0 0x01c05000 0x0 0x1000>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_pll_periph0>, <&clk_spi0>;
clock-frequency = <100000000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&spi0_pins_a &spi0_pins_b &spi0_pins_c>;
pinctrl-1 = <&spi0_pins_d>;
spi0_cs_number = <2>;
spi0_cs_bitmap = <3>;
status = "disabled";
};
spi1: spi@01c06000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "allwinner,sun8i-spi";
device_type = "spi1";
reg = <0x0 0x01c06000 0x0 0x1000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_pll_periph0>, <&clk_spi1>;
clock-frequency = <100000000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&spi1_pins_a &spi1_pins_b>;
pinctrl-1 = <&spi1_pins_c>;
spi1_cs_number = <2>;
spi1_cs_bitmap = <3>;
status = "disabled";
};
spi2: spi@01c17000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "allwinner,sun8i-spi";
device_type = "spi2";
reg = <0x0 0x01c17000 0x0 0x1000>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_pll_periph0>, <&clk_spi2>;
clock-frequency = <100000000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&spi2_pins_a &spi2_pins_b>;
pinctrl-1 = <&spi2_pins_c>;
spi2_cs_number = <2>;
spi2_cs_bitmap = <3>;
status = "disabled";
};
spi3: spi@01c18000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "allwinner,sun8i-spi";
device_type = "spi3";
reg = <0x0 0x01c18000 0x0 0x1000>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_pll_periph0>, <&clk_spi3>;
clock-frequency = <100000000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&spi3_pins_a &spi3_pins_b>;
pinctrl-1 = <&spi3_pins_c>;
spi3_cs_number = <2>;
spi3_cs_bitmap = <3>;
status = "disabled";
};
usbc0:usbc0@0 {
device_type = "usbc0";
compatible = "allwinner,sun50i-otg-manager";
usb_port_type = <2>;
usb_detect_type = <1>;
usb_id_gpio = <&pio PH 9 0 1 1 1>;
usb_det_vbus_gpio = "axp_ctrl";
usb_drv_vbus_gpio = <&axp_pio PP 3 1 1 1 1>;
usb_host_init_state = <0>;
usb_regulator_io = "nocare";
usb_wakeup_suspend = <0>;
usb_luns = <3>;
usb_serial_unique = <0>;
usb_serial_number = "20080411";
rndis_wceis = <1>;
status = "okay";
};
udc:udc-controller@0x01c19000 {
compatible = "allwinner,sun50i-udc";
reg = <0x0 0x01c19000 0x0 0x1000>, /*udc base*/
<0x0 0x01c00000 0x0 0x100>; /*sram base*/
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_usbphy0>, <&clk_usbotg>;
status = "okay";
};
ehci0:ehci0-controller@0x01c1a000 {
compatible = "allwinner,sun50i-ehci0";
reg = <0x0 0x01c1a000 0x0 0xFFF>, /*hci0 base*/
<0x0 0x01c00000 0x0 0x100>, /*sram base*/
<0x0 0x01c19000 0x0 0x1000>; /*otg base*/
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_usbphy0>, <&clk_usbehci0>;
hci_ctrl_no = <0>;
status = "okay";
};
ohci0:ohci0-controller@0x01c1a400 {
compatible = "allwinner,sun50i-ohci0";
reg = <0x0 0x01c1a000 0x0 0xFFF>, /*hci0 base*/
<0x0 0x01c00000 0x0 0x100>, /*sram base*/
<0x0 0x01c19000 0x0 0x1000>; /*otg base*/
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_usbphy0>, <&clk_usbohci0>;
hci_ctrl_no = <0>;
status = "okay";
};
usbc1:usbc1@0 {
device_type = "usbc1";
usb_drv_vbus_gpio = <&pio PB 6 1 1 1 1>;
usb_host_init_state = <1>;
usb_regulator_io = "nocare";
usb_wakeup_suspend = <0>;
/* HISC device */
usb_hsic_used = <0>;
usb_hsic_regulator_io = "vcc-hsic-12";
/*Marvell 4G HSIC */
usb_hsic_ctrl = <0>;
usb_hsic_rdy_gpio;
/* SMSC usb3503 HSIC HUB */
usb_hsic_usb3503_flag = <0>;
usb_hsic_hub_connect_gpio;
usb_hsic_int_n_gpio;
usb_hsic_reset_n_gpio;
status = "okay";
};
codec:codec@0x01c22c00 {
compatible = "allwinner,sunxi-internal-codec";
reg = <0x0 0x01c22c00 0x0 0x2bc>,/*digital baseadress*/
<0x0 0x01c22f00 0x0 0x4>;/*analog baseadress*/
clocks = <&clk_pll_audio>,<&clk_adda>;
/*gpio-spk=<&pio 6 7 0>;*/
gpio-spk = <&pio PB 1 1 1 1 1>;
headphonevol = <0x3b>;
spkervol = <0x1b>;
maingain = <0x4>;
hp_dirused = <0x0>;
pa_sleep_time = <0x15e>;
status = "okay";
};
cpudai:cpudai0-controller@0x01c22c00 {
compatible = "allwinner,sunxi-internal-cpudai";
reg = <0x0 0x01c22c00 0x0 0x2bc>;/*digital baseadress*/
status = "okay";
};
daudio0:daudio@0x01c22000 {
compatible = "allwinner,sunxi-daudio";
reg = <0x0 0x01c22000 0x0 0x70>;
clocks = <&clk_pll_audio>,<&clk_i2s0>;
pinctrl-names = "default","sleep";
pinctrl-0 = <&daudio0_pins_a>;
pinctrl-1 = <&daudio0_pins_b>;
pcm_lrck_period = <0x20>;
pcm_lrckr_period = <0x01>;
slot_width_select = <0x20>;
pcm_lsb_first = <0x0>;
tx_data_mode = <0x0>;
rx_data_mode = <0x0>;
daudio_master = <0x04>;
audio_format = <0x01>;
signal_inversion = <0x01>;
frametype = <0x0>;
tdm_config = <0x01>;
tdm_num = <0x0>;
status = "okay";
};
daudio1:daudio@0x01c22400 {
compatible = "allwinner,sunxi-daudio";
reg = <0x0 0x01c22400 0x0 0x70>;
pinctrl-names = "default","sleep";
pinctrl-0 = <&daudio1_pins_a>;
pinctrl-1 = <&daudio1_pins_b>;
clocks = <&clk_pll_audio>,<&clk_i2s1>;
pcm_lrck_period = <0x20>;
pcm_lrckr_period = <0x01>;
slot_width_select = <0x20>;
pcm_lsb_first = <0x0>;
tx_data_mode = <0x0>;
rx_data_mode = <0x0>;
daudio_master = <0x04>;
audio_format = <0x01>;
signal_inversion = <0x01>;
frametype = <0x0>;
tdm_config = <0x01>;
tdm_num = <0x1>;
status = "okay";
};
daudio2:daudio@0x01c22800{
compatible = "allwinner,sunxi-tdmhdmi";
reg = <0x0 0x01c22800 0x0 0x58>;
clocks = <&clk_pll_audio>,<&clk_i2s2>;
status = "okay";
};
spdif:spdif-controller@0x01c21000{
compatible = "allwinner,sunxi-spdif";
reg = <0x0 0x01c21000 0x0 0x38>;
clocks = <&clk_pll_audio>,<&clk_spdif>;
pinctrl-names = "default","sleep";
pinctrl-0 = <&spdif_pins_a>;
pinctrl-1 = <&spdif_pins_b>;
status = "okay";
};
dsd:dsd-controller@0x01c23400{
compatible = "allwinner,sunxi-dsd";
reg = <0x0 0x01c23400 0x0 0x2c>;
clocks = <&clk_pll_audio>,<&clk_dsd>;
pinctrl-names = "default","sleep";
pinctrl-0 = <&dsd_pins_a>;
pinctrl-1 = <&dsd_pins_b>;
status = "okay";
};
dmic:dmic-controller@0x01c23800{
compatible = "allwinner,sunxi-dmic";
reg = <0x0 0x01c23800 0x0 0x34>;
clocks = <&clk_pll_audio>,<&clk_dmic>;
pinctrl-names = "default","sleep";
pinctrl-0 = <&dmic_pins_a>;
pinctrl-1 = <&dmic_pins_b>;
status = "okay";
};
sndcodec:sound@0 {
compatible = "allwinner,sunxi-codec-machine";
interrupts = <GIC_SPI 28 4>;
sunxi,cpudai-controller = <&cpudai>;
sunxi,audio-codec = <&codec>;
hp_detect_case = <0x00>;
status = "okay";
};
snddaudio0:sound@1{
compatible = "allwinner,sunxi-daudio0-machine";
sunxi,daudio0-controller = <&daudio0>;
status = "okay";
};
snddaudio1:sound@2{
compatible = "allwinner,sunxi-daudio1-machine";
sunxi,daudio1-controller = <&daudio1>;
status = "okay";
};
sndhdmi:sound@3{
compatible = "allwinner,sunxi-hdmi-machine";
sunxi,hdmi-controller = <&daudio2>;
status = "okay";
};
sndspdif:sound@4{
compatible = "allwinner,sunxi-spdif-machine";
sunxi,spdif-controller = <&spdif>;
status = "okay";
};
snddsd:sound@4{
compatible = "allwinner,sunxi-dsd-machine";
sunxi,dsd-controller = <&dsd>;
status = "okay";
};
snddmic:sound@5{
compatible = "allwinner,sunxi-dmic-machine";
sunxi,dmic-controller = <&dmic>;
status = "okay";
};
sdc2: sdmmc@01C11000 {
compatible = "allwinner,sun50i-sdmmc2";
device_type = "sdc2";
reg = <0x0 0x01C11000 0x0 0x1000>;
interrupts = <GIC_SPI 62 0x0104>; /* */
clocks = <&clk_hosc>,<&clk_pll_periph1x2>,<&clk_sdmmc2_mod>,<&clk_sdmmc2_bus>,<&clk_sdmmc2_rst>;
clock-names = "osc24m","pll_periph","mmc","ahb","rst";
pinctrl-names = "default","sleep";
pinctrl-0 = <&sdc2_pins_a>;
pinctrl-1 = <&sdc2_pins_b>;
bus-width = <8>;
/*mmc-ddr-1_8v;*/
/*mmc-hs200-1_8v;*/
/*mmc-hs400-1_8v;*/
/*non-removable;*/
/*max-frequency = <200000000>;*/
max-frequency = <50000000>;
/*-- speed mode --*/
/*sm0: DS26_SDR12*/
/*sm1: HSSDR52_SDR25*/
/*sm2: HSDDR52_DDR50*/
/*sm3: HS200_SDR104*/
/*sm4: HS400*/
/*-- frequency point --
/*f0: CLK_400K*/
/*f1: CLK_25M*/
/*f2: CLK_50M*/
/*f3: CLK_100M*/
/*f4: CLK_150M*/
/*f5: CLK_200M*/
sdc_tm4_sm0_freq0 = <0>;
sdc_tm4_sm0_freq1 = <0>;
sdc_tm4_sm1_freq0 = <0x00000000>;
sdc_tm4_sm1_freq1 = <0>;
sdc_tm4_sm2_freq0 = <0x00000000>;
sdc_tm4_sm2_freq1 = <0>;
sdc_tm4_sm3_freq0 = <0x05000000>;
sdc_tm4_sm3_freq1 = <0x00000005>;
sdc_tm4_sm4_freq0 = <0x00050000>;
sdc_tm4_sm4_freq1 = <0x00000004>;
/*vmmc-supply = <&reg_3p3v>;*/
/*vqmc-supply = <&reg_3p3v>;*/
/*vdmc-supply = <&reg_3p3v>;*/
/*vmmc = "vcc-card";*/
/*vqmc = "";*/
/*vdmc = "";*/
/*sunxi-power-save-mode;*/
/*status = "disabled";*/
status = "okay";
};
sdc0: sdmmc@01c0f000 {
compatible = "allwinner,sun50i-sdmmc0";
device_type = "sdc0";
reg = <0x0 0x01c0f000 0x0 0x1000>; /* only sdmmc0 */
interrupts = <GIC_SPI 60 0x0104>; /* */
clocks = <&clk_hosc>,<&clk_pll_periph1x2>,<&clk_sdmmc0_mod>,<&clk_sdmmc0_bus>,<&clk_sdmmc0_rst>;
clock-names = "osc24m","pll_periph","mmc","ahb","rst";
pinctrl-names = "default","sleep";
pinctrl-0 = <&sdc0_pins_a>;
pinctrl-1 = <&sdc0_pins_b>;
max-frequency = <50000000>;
bus-width = <4>;
broken-cd;
/*cd-inverted*/
cd-gpios = <&pio PF 6 0 1 2 0>;
/* vmmc-supply = <&reg_3p3v>;*/
/* vqmc-supply = <&reg_3p3v>;*/
/* vdmc-supply = <&reg_3p3v>;*/
/*vmmc = "vcc-card";*/
/*vqmc = "";*/
/*vdmc = "";*/
/*sd-uhs-sdr50;*/
/*sd-uhs-ddr50;*/
/*cap-sdio-irq;*/
/*keep-power-in-suspend;*/
/*ignore-pm-notify;*/
/*sunxi-power-save-mode;*/
/*sunxi-dly-400k = <1 0 0 0>; */
/*sunxi-dly-26M = <1 0 0 0>;*/
/*sunxi-dly-52M = <1 0 0 0>;*/
/*sunxi-dly-52M-ddr4 = <1 0 0 0>;*/
/*sunxi-dly-52M-ddr8 = <1 0 0 0>;*/
/*sunxi-dly-104M = <1 0 0 0>;*/
/*sunxi-dly-208M = <1 0 0 0>;*/
/*sunxi-dly-104M-ddr = <1 0 0 0>;*/
/*sunxi-dly-208M-ddr = <1 0 0 0>;*/
status = "okay";
/*status = "disabled";*/
};
sdc1: sdmmc@1C10000 {
compatible = "allwinner,sun50i-sdmmc1";
device_type = "sdc1";
reg = <0x0 0x1C10000 0x0 0x1000>;
interrupts = <GIC_SPI 61 0x0104>; /* */
clocks = <&clk_hosc>,<&clk_pll_periph1x2>,<&clk_sdmmc1_mod>,<&clk_sdmmc1_bus>,<&clk_sdmmc1_rst>;
clock-names = "osc24m","pll_periph","mmc","ahb","rst";
pinctrl-names = "default","sleep";
pinctrl-0 = <&sdc1_pins_a>;
pinctrl-1 = <&sdc1_pins_b>;
max-frequency = <50000000>;
bus-width = <4>;
/*broken-cd;*/
/*cd-inverted*/
/*cd-gpios = <&pio PG 6 6 1 2 0>;*/
/* vmmc-supply = <&reg_3p3v>;*/
/* vqmc-supply = <&reg_3p3v>;*/
/* vdmc-supply = <&reg_3p3v>;*/
/*vmmc = "vcc-card";*/
/*vqmc = "";*/
/*vdmc = "";*/
/*sd-uhs-sdr50;*/
/*sd-uhs-ddr50;*/
/*sd-uhs-sdr104;*/
/*cap-sdio-irq;*/
/*keep-power-in-suspend;*/
/*ignore-pm-notify;*/
/*sunxi-power-save-mode;*/
/*sunxi-dly-400k = <1 0 0 0 0>; */
/*sunxi-dly-26M = <1 0 0 0 0>;*/
/*sunxi-dly-52M = <1 0 0 0 0>;*/
sunxi-dly-52M-ddr4 = <1 0 0 0 2>;
/*sunxi-dly-52M-ddr8 = <1 0 0 0 0>;*/
sunxi-dly-104M = <1 0 0 0 1>;
/*sunxi-dly-208M = <1 1 0 0 0>;*/
sunxi-dly-208M = <1 0 0 0 1>;
/*sunxi-dly-104M-ddr = <1 0 0 0 0>;*/
/*sunxi-dly-208M-ddr = <1 0 0 0 0>;*/
status = "okay";
/*status = "disabled";*/
};
disp: disp@01000000 {
compatible = "allwinner,sun50i-disp";
reg = <0x0 0x01000000 0x0 0x00300000>,/*de*/
<0x0 0x01c0c000 0x0 0x17fc>,/*lcd*/
<0x0 0x01ca0000 0x0 0x10fc>;/*dsi*/
interrupts = <GIC_SPI 86 0x0104>, <GIC_SPI 87 0x0104>,
<GIC_SPI 89 0x0104>;/* for dsi */
clocks = <&clk_de>,<&clk_tcon0>;
status = "okay";
};
lcd0: lcd0@01c0c000 {
compatible = "allwinner,sunxi-lcd0";
pinctrl-names = "active","sleep";
status = "okay";
};
soc_tr: tr@01000000 {
compatible = "allwinner,sun50i-tr";
reg = <0x0 0x01000000 0x0 0x000200bc>;
interrupts = <GIC_SPI 96 0x0104>;
clocks = <&clk_de>;
status = "okay";
};
pwm: pwm@01c21400 {
compatible = "allwinner,sunxi-pwm0";
reg = <0x0 0x01c21400 0x0 0x3c>;
pwm-number = <1>;
pinctrl-names = "active", "sleep";
};
boot_disp: boot_disp {
compatible = "allwinner,boot_disp";
};
csi_cci0:cci@0x01cb3000 {
compatible = "allwinner,sunxi-csi_cci";
reg = <0x0 0x01cb3000 0x0 0x1000>; /*0x01cb3000--0x01cb4000*/
interrupts = <GIC_SPI 85 4>;/*SUNXI_IRQ_CSI0_CCI (SUNXI_GIC_START + 85) = 117*/
status = "disabled";
};
csi_res0:csi_res@0x01c09000 {
compatible = "allwinner,sunxi-csi";
reg = <0x0 0x01c09000 0x0 0x1000>;/*0x01c09000--0x01c0a000*/
status = "okay";
};
csi_res1:csi_res@0X01c1d000 {
compatible = "allwinner,sunxi-csi";
reg = <0x0 0X01c1d000 0x0 0x1000>;/*0X01c1d000--0x01c0e000*/
status = "disabled";
};
csi0:vfe@0 {
device_type= "csi0";
compatible = "allwinner,sunxi-vfe";
interrupts = <GIC_SPI 84 4>;/*SUNXI_IRQ_CSI0 (SUNXI_GIC_START + 84 ) = 116*/
clocks = <&clk_csi_s>, <&clk_csi_m>,
<&clk_pll_periph0>,<&clk_hosc>;
pinctrl-names = "default","sleep";
pinctrl-0 = <&csi0_pins_a>;
pinctrl-1 = <&csi0_pins_b>;
csi0_sensor_list = <0>;
csi0_mck = <&pio PE 1 1 0 1 0>; /*PE1 .mul_sel = 1, .pull = 0, .drv_level = 1, .data = 0*/
status = "okay";
csi0_dev0:dev@0{
csi0_dev0_mname = "ov5640";
csi0_dev0_twi_addr = <0x78>;
csi0_dev0_twi_id = <1>;
csi0_dev0_pos = "rear";
csi0_dev0_isp_used = <1>;
csi0_dev0_fmt = <0>;
csi0_dev0_stby_mode = <0>;
csi0_dev0_vflip = <0>;
csi0_dev0_hflip = <0>;
csi0_dev0_iovdd = "iovdd-csi";
csi0_dev0_iovdd_vol = <2800000>;
csi0_dev0_avdd = "avdd-csi";
csi0_dev0_avdd_vol = <2800000>;
csi0_dev0_dvdd = "dvdd-csi-18";
csi0_dev0_dvdd_vol = <1500000>;
csi0_dev0_afvdd = "afvcc-csi";
csi0_dev0_afvdd_vol = <2800000>;
csi0_dev0_power_en = <>;
csi0_dev0_reset = <&pio PE 14 1 0 1 0>; /*PE14 .mul_sel = 1, .pull = 0, .drv_level = 1, .data = 0*/
csi0_dev0_pwdn = <&pio PE 15 1 0 1 0>; /*PE15 .mul_sel = 1, .pull = 0, .drv_level = 1, .data = 0*/
csi0_dev0_flash_en = <>;
csi0_dev0_flash_mode = <>;
csi0_dev0_af_pwdn = <>;
csi0_dev0_act_used = <0>;
csi0_dev0_act_name = "ad5820_act";
csi0_dev0_act_slave = <0x18>;
status = "okay";
};
csi0_dev1:dev@1{
csi0_dev1_mname = "";
csi0_dev1_twi_addr = <0x78>;
csi0_dev1_twi_id = <1>;
csi0_dev1_pos = "rear";
csi0_dev1_isp_used = <1>;
csi0_dev1_fmt = <0>;
csi0_dev1_stby_mode = <0>;
csi0_dev1_vflip = <0>;
csi0_dev1_hflip = <0>;
csi0_dev1_iovdd = "iovdd-csi";
csi0_dev1_iovdd_vol = <2800000>;
csi0_dev1_avdd = "avdd-csi";
csi0_dev1_avdd_vol = <2800000>;
csi0_dev1_dvdd = "dvdd-csi-18";
csi0_dev1_dvdd_vol = <1500000>;
csi0_dev1_afvdd = "afvcc-csi";
csi0_dev1_afvdd_vol = <2800000>;
csi0_dev1_power_en = <>;
csi0_dev1_reset = <>;
csi0_dev1_pwdn = <>;
csi0_dev1_flash_en = <>;
csi0_dev1_flash_mode = <>;
csi0_dev1_af_pwdn = <>;
csi0_dev1_act_used = <0>;
csi0_dev1_act_name = "ad5820_act";
csi0_dev1_act_slave = <0x18>;
status = "disabled";
};
};
csi1:vfe@1 {
device_type= "csi1";
compatible = "allwinner,sunxi-vfe";
interrupts = <GIC_SPI 84 4>;/*SUNXI_IRQ_CSI1 (SUNXI_GIC_START + 85 ) = 117*/
clocks = <&clk_csi_s>, <&clk_csi_misc>,
<&clk_pll_periph0>,<&clk_hosc>;
pinctrl-names = "default","sleep";
pinctrl-0 = <&csi1_pins_a>;
pinctrl-1 = <&csi1_pins_b>;
csi1_sensor_list = <0>;
csi1_mck = <&pio PG 1 1 0 1 0>; /*PG1 .mul_sel = 1, .pull = 0, .drv_level = 1, .data = 0*/
status = "disabled";
csi1_dev0:dev@0{
csi1_dev0_mname = "ov5640";
csi1_dev0_twi_addr = <0x78>;
csi1_dev0_twi_id = <1>;
csi1_dev0_pos = "rear";
csi1_dev0_isp_used = <1>;
csi1_dev0_fmt = <0>;
csi1_dev0_stby_mode = <0>;
csi1_dev0_vflip = <0>;
csi1_dev0_hflip = <0>;
csi1_dev0_iovdd = "iovdd-csi";
csi1_dev0_iovdd_vol = <2800000>;
csi1_dev0_avdd = "avdd-csi";
csi1_dev0_avdd_vol = <2800000>;
csi1_dev0_dvdd = "dvdd-csi-18";
csi1_dev0_dvdd_vol = <1500000>;
csi1_dev0_afvdd = "afvcc-csi";
csi1_dev0_afvdd_vol = <2800000>;
csi1_dev0_power_en = <>;
csi1_dev0_reset = <&pio PE 14 1 0 1 0>; /*PE14 .mul_sel = 1, .pull = 0, .drv_level = 1, .data = 0*/
csi1_dev0_pwdn = <&pio PE 15 1 0 1 0>; /*PE15 .mul_sel = 1, .pull = 0, .drv_level = 1, .data = 0*/
csi1_dev0_flash_en = <>;
csi1_dev0_flash_mode = <>;
csi1_dev0_af_pwdn = <>;
csi1_dev0_act_used = <0>;
csi1_dev0_act_name = "ad5820_act";
csi1_dev0_act_slave = <0x18>;
status = "disabled";
};
csi1_dev1:dev@1{
csi1_dev1_mname = "";
csi1_dev1_twi_addr = <0x78>;
csi1_dev1_twi_id = <1>;
csi1_dev1_pos = "rear";
csi1_dev1_isp_used = <1>;
csi1_dev1_fmt = <0>;
csi1_dev1_stby_mode = <0>;
csi1_dev1_vflip = <0>;
csi1_dev1_hflip = <0>;
csi1_dev1_iovdd = "iovdd-csi";
csi1_dev1_iovdd_vol = <2800000>;
csi1_dev1_avdd = "avdd-csi";
csi1_dev1_avdd_vol = <2800000>;
csi1_dev1_dvdd = "dvdd-csi-18";
csi1_dev1_dvdd_vol = <1500000>;
csi1_dev1_afvdd = "afvcc-csi";
csi1_dev1_afvdd_vol = <2800000>;
csi1_dev1_power_en = <>;
csi1_dev1_reset = <>;
csi1_dev1_pwdn = <>;
csi1_dev1_flash_en = <>;
csi1_dev1_flash_mode = <>;
csi1_dev1_af_pwdn = <>;
csi1_dev1_act_used = <0>;
csi1_dev1_act_name = "ad5820_act";
csi1_dev1_act_slave = <0x18>;
status = "disabled";
};
};
Vdevice: vdevice@0{
compatible = "allwinner,sun50i-vdevice";
pinctrl-names = "default";
pinctrl-0 = <&vdevice_pins_a>;
status = "okay";
};
cryptoengine: ce@1c15000 {
compatible = "allwinner,sunxi-ce";
reg = <0x0 0x01c15000 0x0 0x80>, /* non-secure space */
<0x0 0x01c15800 0x0 0x80>; /* secure space */
interrupts = <GIC_SPI 94 0xff01>, /* non-secure space */
<GIC_SPI 80 0xff01>; /* secure space */
clock-frequency = <300000000>, /* 300MHz */
<200000000>; /* 200MHz for RSA */
clocks = <&clk_pll_periph0x2>;
};
nmi:nmi@0x01f00c00{
#address-cells = <1>;
#size-cells = <0>;
compatible = "allwinner,sunxi-nmi";
reg = <0x0 0x01f00c00 0x0 0x50>;
nmi_irq_ctrl = <0x0c>;
nmi_irq_en = <0x40>;
nmi_irq_status = <0x10>;
nmi_irq_mask = <0x50>;
status = "okay";
};
pmu0:pmu0@0{
compatible = "allwinner,pmu0";
device_type = "pmu0";
pmu_batdeten = <1>;
pmu_init_chgend_rate = <20>;
pmu_init_chg_enabled = <1>;
pmu_init_adc_freq = <800>;
pmu_init_adcts_freq = <800>;
pmu_init_chg_pretime = <70>;
pmu_init_chg_csttime = <720>;
pmu_batt_cap_correct = <1>;
pmu_chg_end_on_en = <0>;
pmu_pwroff_vol = <3300>;
pmu_pwron_vol = <2600>;
pmu_powkey_off_delay_time = <0>;
pmu_pwrok_time = <64>;
pmu_reset_shutdown_en = <1>;
pmu_restvol_adjust_time = <60>;
pmu_ocv_cou_adjust_time = <60>;
pmu_vbusen_func = <1>;
pmu_reset = <0>;
pmu_IRQ_wakeup = <0>;
pmu_hot_shutdowm = <1>;
pmu_inshort = <0>;
pmu_bat_shutdown_ltf = <3200>; /* add by superm for debug */
pmu_bat_shutdown_htf = <237>; /* add by superm for debug */
status = "okay";
};
pmu0_regu:regu@0{
compatible = "allwinner,pmu0_regu";
regulator_count = <23>;
status = "okay";
};
nand0:nand0@01c03000 {
compatible = "allwinner,sun8iw11-nand";
device_type = "nand0";
reg = <0x0 0x01c03000 0x0 0x1000>; /* nand0 */
interrupts = <GIC_SPI 70 0x04>;
clocks = <&clk_pll_periph0x2>,<&clk_nand>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&nand0_pins_a &nand0_pins_b>;
pinctrl-1 = <&nand0_pins_c>;
nand0_regulator1 = "vcc-nand";
nand0_regulator2 = "none";
nand0_cache_level = <0x55aaaa55>;
nand0_flush_cache_num = <0x55aaaa55>;
nand0_capacity_level = <0x55aaaa55>;
nand0_id_number_ctl = <0x55aaaa55>;
nand0_print_level = <0x55aaaa55>;
nand0_p0 = <0x55aaaa55>;
nand0_p1 = <0x55aaaa55>;
nand0_p2 = <0x55aaaa55>;
nand0_p3 = <0x55aaaa55>;
status = "okay";
};
sunxi_thermal_sensor:thermal_sensor{
compatible = "allwinner,thermal_sensor";
reg = <0x0 0x01c25000 0x0 0x400>;
interrupts = <GIC_SPI 31 IRQ_TYPE_NONE>;
clocks = <&clk_hosc>,<&clk_ths>;
sensor_num = <3>;
shut_temp= <120>;
status = "okay";
combine0:combine0{
#thermal-sensor-cells = <1>;
combine_cnt = <3>;
combine_type = "max";
combine_chn = <0 1 2>;
};
};
cpu_budget_cooling:cpu_budget_cool{
compatible = "allwinner,budget_cooling";
#cooling-cells = <2>;
status = "okay";
state_cnt = <7>;
cluster_num = <1>;
state0 = <1152000 4>;
state1 = <1104000 4>;
state2 = <1008000 4>;
state3 = <816000 4>;
state4 = <648000 4>;
state5 = <648000 2>;
state6 = <648000 1>;
};
gpu_cooling:gpu_cooling{
compatible = "allwinner,gpu_cooling";
reg = <0x0 0x0 0x0 0x0>;
#cooling-cells = <2>;
status = "okay";
state_cnt = <3>;
state0 = <0>;
state1 = <360>;
state2 = <144>;
};
thermal-zones{
soc_thermal{
polling-delay-passive = <500>;
polling-delay = <2000>;
thermal-sensors = <&combine0 0>;
trips{
cpu_trip0:t0{
temperature = <65>;
type = "passive";
hysteresis = <0>;
};
cpu_trip1:t1{
temperature = <80>;
type = "passive";
hysteresis = <0>;
};
cpu_trip2:t2{
temperature = <90>;
type = "passive";
hysteresis = <0>;
};
cpu_trip3:t3{
temperature = <100>;
type = "passive";
hysteresis = <0>;
};
gpu_trip0:t4{
temperature = <85>;
type = "passive";
hysteresis = <0>;
};
gpu_trip1:t5{
temperature = <95>;
type = "passive";
hysteresis = <0>;
};
crt_trip:t6{
temperature = <110>;
type = "critical";
hysteresis = <0>;
};
};
cooling-maps{
bind0{
contribution = <0>;
trip = <&cpu_trip0>;
cooling-device = <&cpu_budget_cooling 1 1>;
};
bind1{
contribution = <0>;
trip = <&cpu_trip1>;
cooling-device = <&cpu_budget_cooling 2 2>;
};
bind2{
contribution = <0>;
trip = <&cpu_trip2>;
cooling-device = <&cpu_budget_cooling 3 4>;
};
bind3{
contribution = <0>;
trip = <&cpu_trip3>;
cooling-device = <&cpu_budget_cooling 5 6>;
};
bind4{
contribution = <0>;
trip = <&gpu_trip0>;
cooling-device = <&gpu_cooling 1 1>;
};
bind5{
contribution = <0>;
trip = <&gpu_trip1>;
cooling-device = <&gpu_cooling 2 2>;
};
};
};
};
keyboard0:keyboard{
compatible = "allwinner,keyboard_2000mv";
reg = <0x0 0x01c21800 0x0 0x400>;
interrupts = <GIC_SPI 30 IRQ_TYPE_NONE>;
status = "okay";
key_cnt = <5>;
key1 = <240 115>;
key2 = <500 114>;
key3 = <700 139>;
key4 = <890 28>;
key5 = <2000 102>;
};
};
};
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